OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

2015-11-24 Michael Collison <michael.collison@linaro.org>

Browse Source 
* config/aarch64/aarch64-simd.md (widen_ssum, widen_usum)
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): New patterns
	* config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes.
	* gcc.target/aarch64/saddw-1.c: New test.
	* gcc.target/aarch64/saddw-2.c: New test.
	* gcc.target/aarch64/uaddw-1.c: New test.
	* gcc.target/aarch64/uaddw-2.c: New test.
	* gcc.target/aarch64/uaddw-3.c: New test.
	* lib/target-support.exp
	(check_effective_target_vect_widen_sum_hi_to_si_pattern):
	Add aarch64 to list of support targets.

From-SVN: r230853
This commit is contained in:
Michael Collison 2015-11-25 06:51:55 +00:00 committed by Michael Collison
parent 17a0986a9b
commit b1b49824a8
10 changed files with 179 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2015-11-24 Michael Collison <michael.collison@linaro.org>
* config/aarch64/aarch64-simd.md (widen_ssum, widen_usum)
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): New patterns
* config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes.
2015-11-24 Steve Ellcey <sellcey@imgtec.com>
* frame-header-opt.c (gate): Check for optimize > 0.

68
gcc/config/aarch64/aarch64-simd.md
View File

@ -2777,6 +2777,62 @@
;; <su><addsub>w<q>.
(define_expand "widen_ssum<mode>3"
[(set (match_operand:<VDBLW> 0 "register_operand" "")
(plus:<VDBLW> (sign_extend:<VDBLW>
(match_operand:VQW 1 "register_operand" ""))
(match_operand:<VDBLW> 2 "register_operand" "")))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
emit_insn (gen_aarch64_saddw<mode>_internal (temp, operands[2],
operands[1], p));
emit_insn (gen_aarch64_saddw2<mode> (operands[0], temp, operands[1]));
DONE;
}
)
(define_expand "widen_ssum<mode>3"
[(set (match_operand:<VWIDE> 0 "register_operand" "")
(plus:<VWIDE> (sign_extend:<VWIDE>
(match_operand:VD_BHSI 1 "register_operand" ""))
(match_operand:<VWIDE> 2 "register_operand" "")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_saddw<mode> (operands[0], operands[2], operands[1]));
DONE;
})
(define_expand "widen_usum<mode>3"
[(set (match_operand:<VDBLW> 0 "register_operand" "")
(plus:<VDBLW> (zero_extend:<VDBLW>
(match_operand:VQW 1 "register_operand" ""))
(match_operand:<VDBLW> 2 "register_operand" "")))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
emit_insn (gen_aarch64_uaddw<mode>_internal (temp, operands[2],
operands[1], p));
emit_insn (gen_aarch64_uaddw2<mode> (operands[0], temp, operands[1]));
DONE;
}
)
(define_expand "widen_usum<mode>3"
[(set (match_operand:<VWIDE> 0 "register_operand" "")
(plus:<VWIDE> (zero_extend:<VWIDE>
(match_operand:VD_BHSI 1 "register_operand" ""))
(match_operand:<VWIDE> 2 "register_operand" "")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_uaddw<mode> (operands[0], operands[2], operands[1]));
DONE;
})
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
@ -2787,6 +2843,18 @@
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")

12
gcc/config/aarch64/iterators.md
View File

@ -479,6 +479,13 @@
(V4SF "V2SF") (V4HF "V2HF")
(V8HF "V4HF") (V2DF "DF")])
;; Half modes of all vector modes, in lower-case.
(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
(V4HI "v2hi") (V8HI "v4hi")
(V2SI "si") (V4SI "v2si")
(V2DI "di") (V2SF "sf")
(V4SF "v2sf") (V2DF "df")])
;; Double modes of vector modes.
(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
(V4HF "V8HF")
@ -496,6 +503,11 @@
(SI "v2si") (DI "v2di")
(DF "v2df")])
;; Modes with double-width elements.
(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
(V4HI "V2SI") (V8HI "V4SI")
(V2SI "DI") (V4SI "V2DI")])
;; Narrowed modes for VDN.
(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
(DI "V2SI")])

11
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,14 @@
2015-11-24 Michael Collison <michael.collison@linaro.org>
* gcc.target/aarch64/saddw-1.c: New test.
* gcc.target/aarch64/saddw-2.c: New test.
* gcc.target/aarch64/uaddw-1.c: New test.
* gcc.target/aarch64/uaddw-2.c: New test.
* gcc.target/aarch64/uaddw-3.c: New test.
* lib/target-support.exp
(check_effective_target_vect_widen_sum_hi_to_si_pattern):
Add aarch64 to list of support targets.
2015-11-24 Steve Ellcey <sellcey@imgtec.com>
* gcc.target/mips/frame-header-4.c: New test.

16
gcc/testsuite/gcc.target/aarch64/saddw-1.c Normal file
View File

@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
int
t6(int len, void * dummy, short * __restrict x)
{
len = len & ~31;
int result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
/* { dg-final { scan-assembler "saddw" } } */
/* { dg-final { scan-assembler "saddw2" } } */

16
gcc/testsuite/gcc.target/aarch64/saddw-2.c Normal file
View File

@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
int
t6(int len, void * dummy, int * __restrict x)
{
len = len & ~31;
long long result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
/* { dg-final { scan-assembler "saddw" } } */
/* { dg-final { scan-assembler "saddw2" } } */

16
gcc/testsuite/gcc.target/aarch64/uaddw-1.c Normal file
View File

@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
int
t6(int len, void * dummy, unsigned short * __restrict x)
{
len = len & ~31;
unsigned int result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
/* { dg-final { scan-assembler "uaddw" } } */
/* { dg-final { scan-assembler "uaddw2" } } */

17
gcc/testsuite/gcc.target/aarch64/uaddw-2.c Normal file
View File

@ -0,0 +1,17 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
int
t6(int len, void * dummy, unsigned short * __restrict x)
{
len = len & ~31;
unsigned int result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
/* { dg-final { scan-assembler "uaddw" } } */
/* { dg-final { scan-assembler "uaddw2" } } */

16
gcc/testsuite/gcc.target/aarch64/uaddw-3.c Normal file
View File

@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
int
t6(int len, void * dummy, char * __restrict x)
{
len = len & ~31;
unsigned short result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
/* { dg-final { scan-assembler "uaddw" } } */
/* { dg-final { scan-assembler "uaddw2" } } */

1
gcc/testsuite/lib/target-supports.exp
View File

@ -4163,6 +4163,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
} else {
set et_vect_widen_sum_hi_to_si_pattern_saved 0
if { [istarget powerpc*-*-*]
|| [istarget aarch64*-*-*]
|| [istarget ia64-*-*] } {
set et_vect_widen_sum_hi_to_si_pattern_saved 1
}