re PR target/78904 (zero-extracts are not effective)
PR target/78904 * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use nonimmediate_operand instead of nonimmediate_x64nomem_operand. (*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1) (*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand instead of general_x64nomem_operand. * config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove. (general_x64nomem_operand): Ditto. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-2.c: New test. From-SVN: r243933
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Uros Bizjak
Uros Bizjak
parent
2226492f26
commit
b1d3a450be
@ -1,3 +1,14 @@
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2016-12-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use
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nonimmediate_operand instead of nonimmediate_x64nomem_operand.
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(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
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(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand
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instead of general_x64nomem_operand.
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* config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove.
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(general_x64nomem_operand): Ditto.
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2016-12-26 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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@ -1295,7 +1295,7 @@
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(define_insn "*cmpqi_ext_1"
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[(set (reg FLAGS_REG)
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(compare
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(match_operand:QI 0 "nonimmediate_x64nomem_operand" "Q,m")
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(match_operand:QI 0 "nonimmediate_operand" "Q,m")
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(subreg:QI
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(zero_extract:SI
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(match_operand 1 "ext_register_operand" "Q,Q")
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@ -1340,7 +1340,7 @@
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(match_operand 0 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_x64nomem_operand" "Qn,m")))]
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(match_operand:QI 1 "general_operand" "Qn,m")))]
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"ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\t{%1, %h0|%h0, %1}"
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[(set_attr "isa" "*,nox64")
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@ -2781,7 +2781,7 @@
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(set_attr "mode" "SI")])
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(define_insn "*extvqi"
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[(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
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(sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q")
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(const_int 8)
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(const_int 8)))]
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@ -2836,7 +2836,7 @@
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(set_attr "mode" "SI")])
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(define_insn "*extzvqi"
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[(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
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(subreg:QI
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
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(const_int 8)
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@ -2897,7 +2897,7 @@
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[(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q")
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(const_int 8)
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(const_int 8))
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(match_operand:SWI248 1 "general_x64nomem_operand" "Qn,m"))]
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(match_operand:SWI248 1 "general_operand" "Qn,m"))]
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""
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{
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if (CONST_INT_P (operands[1]))
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@ -6087,7 +6087,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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{
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@ -7889,7 +7889,7 @@
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(zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_x64nomem_operand" "Qn,m"))
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(match_operand:QI 1 "general_operand" "Qn,m"))
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(const_int 0)))]
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"ix86_match_ccmode (insn, CCNOmode)"
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"test{b}\t{%1, %h0|%h0, %1}"
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@ -8417,7 +8417,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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"and{b}\t{%2, %h0|%h0, %2}"
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@ -8803,7 +8803,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"<logic>{b}\t{%2, %h0|%h0, %2}"
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@ -8913,7 +8913,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_x64nomem_operand" "Qn,m"))
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(match_operand:QI 2 "general_operand" "Qn,m"))
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(const_int 0)))
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(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
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(const_int 8)
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@ -100,18 +100,6 @@
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&& (REGNO (op) > LAST_VIRTUAL_REGISTER || QI_REGNO_P (REGNO (op))));
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})
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;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
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(define_predicate "nonimmediate_x64nomem_operand"
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(if_then_else (match_test "TARGET_64BIT")
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(match_operand 0 "register_operand")
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(match_operand 0 "nonimmediate_operand")))
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;; Match general operands, but exclude memory operands on 64bit targets.
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(define_predicate "general_x64nomem_operand"
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(if_then_else (match_test "TARGET_64BIT")
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(match_operand 0 "nonmemory_operand")
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(match_operand 0 "general_operand")))
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;; Match register operands, but include memory operands for TARGET_SSE_MATH.
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(define_predicate "register_ssemem_operand"
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(if_then_else
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@ -1,7 +1,12 @@
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2016-12-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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* gcc.target/i386/pr78904-2.c: New test.
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2016-12-26 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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* gcc.target/i386/pr78904.c: New test.
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* gcc.target/i386/pr78904-1.c: New test.
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2016-12-23 Andre Vehreschild <vehre@gcc.gnu.org>
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48
gcc/testsuite/gcc.target/i386/pr78904-2.c
Normal file
48
gcc/testsuite/gcc.target/i386/pr78904-2.c
Normal file
@ -0,0 +1,48 @@
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/* PR target/78904 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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struct S1
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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extern struct S1 t;
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struct S1 test_and (struct S1 a, struct S1 b)
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{
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a.val &= b.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]andb\[^\n\r]*, %.h" } } */
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struct S1 test_or (struct S1 a, struct S1 b)
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{
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a.val |= b.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]orb\[^\n\r]*, %.h" } } */
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struct S1 test_xor (struct S1 a, struct S1 b)
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{
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a.val ^= b.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]xorb\[^\n\r]*, %.h" } } */
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struct S1 test_add (struct S1 a, struct S1 b)
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{
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a.val += t.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]addb\[^\n\r]*, %.h" } } */
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