Factor out common tests in 8-byte reg/reg move splitters on 32-bit sparc.
* config/sparc/sparc.c (sparc_split_regreg_legitimate): New function. * config/sparc/sparc-protos.h (sparc_split_regreg_legitimate): Declare it. * config/sparc/sparc.md (DImode reg/reg split): Use it. (DFmode reg/reg split): Likewise. From-SVN: r180354
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@ -1,5 +1,12 @@
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2011-10-23 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.c (sparc_split_regreg_legitimate): New
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function.
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* config/sparc/sparc-protos.h (sparc_split_regreg_legitimate):
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Declare it.
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* config/sparc/sparc.md (DImode reg/reg split): Use it.
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(DFmode reg/reg split): Likewise.
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* config/sparc/sparc.md (*movdi_insn_sp32_v9): Add alternatives for
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generating fzero and fone instructions.
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(DImode const_int --> reg splitter): Only trigger for integer regs.
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@ -68,6 +68,7 @@ extern void sparc_defer_case_vector (rtx, rtx, int);
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extern bool sparc_expand_move (enum machine_mode, rtx *);
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extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
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extern int sparc_splitdi_legitimate (rtx, rtx);
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extern int sparc_split_regreg_legitimate (rtx, rtx);
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extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
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extern const char *output_ubranch (rtx, int, rtx);
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extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
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@ -7762,6 +7762,31 @@ sparc_splitdi_legitimate (rtx reg, rtx mem)
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return 1;
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}
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/* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
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int
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sparc_split_regreg_legitimate (rtx reg1, rtx reg2)
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{
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int regno1, regno2;
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if (GET_CODE (reg1) == SUBREG)
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reg1 = SUBREG_REG (reg1);
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if (GET_CODE (reg1) != REG)
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return 0;
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regno1 = REGNO (reg1);
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if (GET_CODE (reg2) == SUBREG)
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reg2 = SUBREG_REG (reg2);
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if (GET_CODE (reg2) != REG)
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return 0;
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regno2 = REGNO (reg2);
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if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2))
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return 1;
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return 0;
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}
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/* Return 1 if x and y are some kind of REG and they refer to
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different hard registers. This test is guaranteed to be
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run after reload. */
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@ -1834,11 +1834,8 @@
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"reload_completed
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&& (! TARGET_V9
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|| (! TARGET_ARCH64
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&& ((GET_CODE (operands[0]) == REG
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&& SPARC_INT_REG_P (REGNO (operands[0])))
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))"
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&& sparc_split_regreg_legitimate (operands[0],
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operands[1])))"
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[(clobber (const_int 0))]
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{
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rtx set_dest = operands[0];
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@ -2247,11 +2244,8 @@
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(match_operand:DF 1 "register_operand" ""))]
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"(! TARGET_V9
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|| (! TARGET_ARCH64
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&& ((GET_CODE (operands[0]) == REG
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&& SPARC_INT_REG_P (REGNO (operands[0])))
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))
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&& sparc_split_regreg_legitimate (operands[0],
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operands[1])))
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&& reload_completed"
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[(clobber (const_int 0))]
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{
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