[AArch64] Add SVE conditional floating-point unary patterns
This patch adds patterns to match conditional unary operations on floating-point modes. At the moment we rely on combine to merge separate arithmetic and vcond_mask operations, and since the latter doesn't accept zero operands, we miss out on the opportunity to use the movprfx /z alternative. (This alternative is tested by the ACLE patches though.) 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org> gcc/ * config/aarch64/aarch64-sve.md (*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_2): New pattern. (*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/cond_unary_1.c: Add tests for floating-point types. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4.c: Likewise. Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org> From-SVN: r274477
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
3c9f496337
commit
b21f7d5309
@ -1,3 +1,10 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* config/aarch64/aarch64-sve.md
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(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_2): New pattern.
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(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_any): Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -1624,6 +1624,62 @@
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"<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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)
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;; Predicated floating-point unary arithmetic, merging with the first input.
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(define_insn_and_rewrite "*cond_<optab><mode>_2"
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[(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(unspec:SVE_F
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[(match_operand 3)
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(match_operand:SI 4 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "0, w")]
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SVE_COND_FP_UNARY)
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE && aarch64_sve_pred_dominates_p (&operands[3], operands[1])"
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"@
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<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>
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movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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"&& !rtx_equal_p (operands[1], operands[3])"
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{
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operands[3] = copy_rtx (operands[1]);
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}
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated floating-point unary arithmetic, merging with an independent
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;; value.
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;;
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;; The earlyclobber isn't needed for the first alternative, but omitting
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;; it would only help the case in which operands 2 and 3 are the same,
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;; which is handled above rather than here. Marking all the alternatives
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;; as earlyclobber helps to make the instruction more regular to the
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;; register allocator.
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_F 0 "register_operand" "=&w, ?&w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(unspec:SVE_F
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[(match_operand 4)
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(match_operand:SI 5 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "w, w, w")]
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SVE_COND_FP_UNARY)
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(match_operand:SVE_F 3 "aarch64_simd_reg_or_zero" "0, Dz, w")]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& !rtx_equal_p (operands[2], operands[3])
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&& aarch64_sve_pred_dominates_p (&operands[4], operands[1])"
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"@
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<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>
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movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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"&& !rtx_equal_p (operands[1], operands[4])"
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{
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operands[4] = copy_rtx (operands[1]);
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}
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[(set_attr "movprfx" "*,yes,yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [PRED] Inverse
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;; -------------------------------------------------------------------------
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@ -1,3 +1,12 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* gcc.target/aarch64/sve/cond_unary_1.c: Add tests for
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floating-point types.
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* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_3.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_4.c: Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -15,15 +15,22 @@
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r[i] = pred[i] ? OP (a[i]) : a[i]; \
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}
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#define TEST_TYPE(T, TYPE) \
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#define TEST_INT_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \
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T (TYPE, __builtin_fabs##SUFFIX) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_INT_TYPE (T, int8_t) \
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TEST_INT_TYPE (T, int16_t) \
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TEST_INT_TYPE (T, int32_t) \
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TEST_INT_TYPE (T, int64_t) \
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TEST_FLOAT_TYPE (T, _Float16, f16) \
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TEST_FLOAT_TYPE (T, float, f) \
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TEST_FLOAT_TYPE (T, double, )
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TEST_ALL (DEF_LOOP)
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@ -37,6 +44,14 @@ TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* XFAILed because the ?: gets canonicalized so that the operation is in
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@ -16,15 +16,22 @@
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r[i] = pred[i] ? OP (a[i]) : b[i]; \
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}
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#define TEST_TYPE(T, TYPE) \
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#define TEST_INT_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \
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T (TYPE, __builtin_fabs##SUFFIX) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_INT_TYPE (T, int8_t) \
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TEST_INT_TYPE (T, int16_t) \
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TEST_INT_TYPE (T, int32_t) \
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TEST_INT_TYPE (T, int64_t) \
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TEST_FLOAT_TYPE (T, _Float16, f16) \
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TEST_FLOAT_TYPE (T, float, f) \
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TEST_FLOAT_TYPE (T, double, )
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TEST_ALL (DEF_LOOP)
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@ -38,6 +45,17 @@ TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* At the moment we don't manage to avoid using MOVPRFX for the
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floating-point functions. */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\t} 6 } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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@ -15,15 +15,22 @@
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r[i] = pred[i] ? OP (a[i]) : 5; \
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}
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#define TEST_TYPE(T, TYPE) \
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#define TEST_INT_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \
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T (TYPE, __builtin_fabs##SUFFIX) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_INT_TYPE (T, int8_t) \
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TEST_INT_TYPE (T, int16_t) \
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TEST_INT_TYPE (T, int32_t) \
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TEST_INT_TYPE (T, int64_t) \
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TEST_FLOAT_TYPE (T, _Float16, f16) \
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TEST_FLOAT_TYPE (T, float, f) \
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TEST_FLOAT_TYPE (T, double, )
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TEST_ALL (DEF_LOOP)
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@ -37,7 +44,15 @@ TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 14 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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@ -15,15 +15,22 @@
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r[i] = pred[i] ? OP (a[i]) : 0; \
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}
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#define TEST_TYPE(T, TYPE) \
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#define TEST_INT_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \
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T (TYPE, __builtin_fabs##SUFFIX) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_INT_TYPE (T, int8_t) \
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TEST_INT_TYPE (T, int16_t) \
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TEST_INT_TYPE (T, int32_t) \
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TEST_INT_TYPE (T, int64_t) \
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TEST_FLOAT_TYPE (T, _Float16, f16) \
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TEST_FLOAT_TYPE (T, float, f) \
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TEST_FLOAT_TYPE (T, double, )
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TEST_ALL (DEF_LOOP)
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@ -37,11 +44,19 @@ TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* Really we should be able to use MOVPRFX /z here, but at the moment
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we're relying on combine to merge a SEL and an arithmetic operation,
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and the SEL doesn't allow the "false" value to be zero when the "true"
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value is a register. */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 14 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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