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Adding GCC port for National Semicondutor's CR16 architecture

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Co-Authored-By: Jayant R Sonar <jayant.sonar@kpitcummins.com>

From-SVN: r183832
This commit is contained in:
Sumanth G 2012-02-02 10:20:32 +00:00 committed by Jayant Sonar
parent 903e49f520
commit b25364a0b9
31 changed files with 7171 additions and 8 deletions
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6
ChangeLog
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@ -1,3 +1,9 @@
2012-02-02 Sumanth G <sumanth.gundapaneni@kpitcummins.com>
Jayant R Sonar <jayant.sonar@kpitcummins.com>
* configure.ac (cr16-*-*): Remove nonconfigdirs.
* configure: Regenerate.
2012-01-23 Harshit Chopra <harshit@google.com>
* MAINTAINERS (Write After Approval): Add myself.

3
configure vendored
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@ -3453,9 +3453,6 @@ case "${target}" in
tic54x-*-*)
noconfigdirs="$noconfigdirs target-libgloss gdb"
;;
cr16-*-*)
noconfigdirs="$noconfigdirs gdb"
;;
d10v-*-*)
noconfigdirs="$noconfigdirs target-libgloss"
;;

3
configure.ac
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@ -879,9 +879,6 @@ case "${target}" in
tic54x-*-*)
noconfigdirs="$noconfigdirs target-libgloss gdb"
;;
cr16-*-*)
noconfigdirs="$noconfigdirs gdb"
;;
d10v-*-*)
noconfigdirs="$noconfigdirs target-libgloss"
;;

5
contrib/ChangeLog
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@ -1,3 +1,8 @@
2012-02-02 Sumanth G <sumanth.gundapaneni@kpitcummins.com>
Jayant R Sonar <jayant.sonar@kpitcummins.com>
* config-list.mk (LIST): Add cr16-elf.
2012-01-02 Georg-Johann Lay <avr@gjlay.de>
PR target/51345

2
contrib/config-list.mk
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@ -18,7 +18,7 @@ LIST = alpha-linux-gnu alpha-freebsd6 alpha-netbsd alpha-openbsd \
arm-linux-androideabi arm-uclinux_eabi arm-ecos-elf arm-eabi \
arm-symbianelf arm-rtems arm-elf arm-wince-pe avr-rtems avr-elf \
bfin-elf bfin-uclinux bfin-linux-uclibc bfin-rtems bfin-openbsd \
c6x-elf c6x-uclinux cris-elf cris-linux crisv32-elf crisv32-linux \
c6x-elf c6x-uclinux cr16-elf cris-elf cris-linux crisv32-elf crisv32-linux \
epiphany-elf epiphany-elfOPT-with-stack-offset=16 fido-elf \
fr30-elf frv-elf frv-linux h8300-elf h8300-rtems hppa-linux-gnu \
hppa-linux-gnuOPT-enable-sjlj-exceptions=yes hppa64-linux-gnu \

20
gcc/ChangeLog
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@ -1,3 +1,23 @@
2012-02-02 Sumanth G <sumanth.gundapaneni@kpitcummins.com>
Jayant R Sonar <jayant.sonar@kpitcummins.com>
* config.gcc: Add cr16-* support.
* doc/extend.texi: Document cr16 extensions.
* doc/install.texi: Document cr16 install.
* doc/invoke.texi: Document cr16 options.
* doc/md.texi: Document cr16 constraints.
* common/config/cr16/cr16-common.c: New file.
* config/cr16/cr16.c: New file.
* config/cr16/cr16.h: New file.
* config/cr16/cr16.md: New file.
* config/cr16/cr16.opt: New file.
* config/cr16/cr16-protos.h: New file.
* config/cr16/predicates.md: New file.
* config/cr16/constraints.md: New file.
* config/cr16/t-cr16: New file.
2012-02-02 Jakub Jelinek <jakub@redhat.com>
PR target/52086

37
gcc/common/config/cr16/cr16-common.c Normal file
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@ -0,0 +1,37 @@
/* Common hooks for CR16.
Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options cr16_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE cr16_option_optimization_table
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

5
gcc/config.gcc
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@ -944,6 +944,11 @@ bfin*-*)
use_collect2=no
use_gcc_stdint=wrap
;;
cr16-*-elf)
tm_file="elfos.h ${tm_file}"
tmake_file="${tmake_file} cr16/t-cr16 "
use_collect2=no
;;
crisv32-*-elf | crisv32-*-none)
tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
tmake_file="cris/t-cris"

81
gcc/config/cr16/constraints.md Normal file
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@ -0,0 +1,81 @@
;; Predicates of machine description for CR16.
;; Copyright (C) 2012 Free Software Foundation, Inc.
;; Contributed by KPIT Cummins Infosystems Limited.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Constraints
;; Register constraints
(define_register_constraint "b" "NOSP_REGS"
"@no sp registers")
(define_register_constraint "c" "SHORT_REGS"
"@short registers")
(define_register_constraint "d" "LONG_REGS"
"@long registers")
;; Integer constraints.
(define_constraint "I"
"A signed 4-bit immediate."
(and (match_code "const_int")
(match_test "SIGNED_INT_FITS_N_BITS (ival, 4)")))
(define_constraint "J"
"A signed 5-bit immediate."
(and (match_code "const_int")
(match_test "SIGNED_INT_FITS_N_BITS (ival, 5)")))
(define_constraint "K"
"A signed 6-bit immediate."
(and (match_code "const_int")
(match_test "SIGNED_INT_FITS_N_BITS (ival, 6)")))
(define_constraint "L"
"A unsigned 4-bit immediate."
(and (match_code "const_int")
(match_test "UNSIGNED_INT_FITS_N_BITS (ival, 4)")))
(define_constraint "M"
"A unsigned and customized 4-bit immediate."
(and (match_code "const_int")
(match_test "(IN_RANGE_P (ival, 0, 15) && ((ival != 9) && (ival != 11)))")))
(define_constraint "N"
"A signed 16-bit immediate."
(and (match_code "const_int")
(match_test "IN_RANGE_P (ival, -32768, 32767)")))
(define_constraint "O"
"A unsigned 20-bit immediate."
(and (match_code "const_int")
(match_test "IN_RANGE_P (ival, 0, 1048575)")))
(define_constraint "Q"
"A shift QI immediate."
(and (match_code "const_int")
(match_test "IN_RANGE_P (ival, 0, 7)")))
(define_constraint "R"
"A shift HI immediate."
(and (match_code "const_int")
(match_test "IN_RANGE_P (ival, 0, 15)")))
(define_constraint "S"
"A shift SI immediate."
(and (match_code "const_int")
(match_test "IN_RANGE_P (ival, 0, 31)")))

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gcc/config/cr16/cr16-protos.h Normal file
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/* Prototypes for exported functions defined in cr16.c
Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Limited.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_CR16_PROTOS_H
#define GCC_CR16_PROTOS_H
#include "target.h"
/* Register usage. */
extern enum reg_class cr16_regno_reg_class (int);
extern int cr16_hard_regno_mode_ok (int regno, enum machine_mode);
/* Passing function arguments. */
extern int cr16_function_arg_regno_p (int);
#ifdef TREE_CODE
#ifdef RTX_CODE
extern void cr16_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
#endif /* RTX_CODE. */
#endif /* TREE_CODE. */
/* Enumeration giving the various data models we support. */
enum data_model_type
{
DM_DEFAULT, /* Default data model (in CR16C/C+ - up to 16M). */
DM_NEAR, /* Near data model (in CR16C/C+ - up to 1M). */
DM_FAR, /* Far data model (in CR16C+ - up to 4G)
(in CR16C - up to 16M). */
ILLEGAL_DM /* Illegal data model. */
};
#ifdef RTX_CODE
/* Addressing Modes. */
struct cr16_address
{
rtx base; /* Base register: Any register or register pair. */
rtx index; /* Index register: If one is present. */
rtx disp; /* Displacement or Absolute address. */
enum data_model_type data; /* data ref type. */
int code; /* Whether the address is code address.
0 - data, 1 - code label, 2 - function label. */
};
enum cr16_addrtype
{
CR16_INVALID,
CR16_REG_REL,
CR16_REGP_REL,
CR16_INDEX_REGP_REL,
CR16_ABSOLUTE
};
extern void notice_update_cc PARAMS ((rtx));
extern int cr16_operand_bit_pos (int val, int bitval);
extern void cr16_decompose_const (rtx x, int *code,
enum data_model_type *data,
bool treat_as_const);
extern enum cr16_addrtype cr16_decompose_address (rtx addr,
struct cr16_address *out,
bool debug_print,
bool treat_as_const);
extern int cr16_const_double_ok (rtx op);
extern int legitimate_pic_operand_p (rtx);
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
#endif /* RTX_CODE. */
/* Prologue/Epilogue functions. */
extern int cr16_initial_elimination_offset (int, int);
extern char *cr16_prepare_push_pop_string (int);
extern void cr16_expand_prologue (void);
extern void cr16_expand_epilogue (void);
extern const char *cr16_emit_add_sub_di (rtx *, enum rtx_code);
extern const char *cr16_emit_logical_di (rtx *, enum rtx_code);
/* Handling the "interrupt" attribute. */
extern int cr16_interrupt_function_p (void);
extern bool cr16_is_data_model (enum data_model_type);
#endif /* Not GCC_CR16_PROTOS_H. */

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gcc/config/cr16/cr16.h Normal file
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/* Definitions of target machine for GNU compiler, for CR16.
Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Limited.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_CR16_H
#define GCC_CR16_H
#define OBJECT_FORMAT_ELF
/* Controlling the driver. */
/* The GNU C++ standard library requires that these macros be defined. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
#undef MATH_LIBRARY
#define MATH_LIBRARY ""
#undef LIB_SPEC
#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
%{msim*:%{!T*:-Tsim.ld}} \
%{!T*:%{!msim*: %{-Telf32cr16.x}}}"
/* Run-time target specification. */
#ifndef TARGET_CPU_CPP_BUILTINS
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define ("__CR__"); \
builtin_define ("__CR16__"); \
builtin_define ("__CR16C__"); \
if (TARGET_CR16CP) \
builtin_define ("__CR16CP__"); \
else \
builtin_define ("__CR16CSTD__"); \
if (CR16_TARGET_DATA_NEAR) \
builtin_define ("__DATA_NEAR__"); \
if (CR16_TARGET_DATA_MEDIUM) \
builtin_define ("__DATA_MEDIUM__"); \
if (CR16_TARGET_DATA_FAR) \
builtin_define ("__DATA_FAR__"); \
if (TARGET_INT32) \
builtin_define ("__INT32__"); \
} \
while (0)
#endif
/* Force the generation of dwarf .debug_frame sections even if not
compiling -g. This guarantees that we can unwind the stack. */
#define DWARF2_FRAME_INFO 1
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* Generate .file/.loc directives, so that the assembler generates the
line table. */
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#define CR16_TARGET_DATA_NEAR cr16_is_data_model (DM_NEAR)
#define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT)
#define CR16_TARGET_DATA_FAR cr16_is_data_model (DM_FAR)
/* Storage layout. */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define UNITS_PER_WORD 2
/* Units per 32-bit (DWORD). */
#define CR16_UNITS_PER_DWORD 4
#define POINTER_SIZE 32
#define PARM_BOUNDARY 16
#define STACK_BOUNDARY (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY))
#define FUNCTION_BOUNDARY BIGGEST_ALIGNMENT
/* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based
where as CR16C is proprietary internal bus architecture. */
#define BIGGEST_ALIGNMENT ((TARGET_CR16CP) ? 32 : 16)
#define MAX_FIXED_MODE_SIZE 64
/* In CR16 arrays of chars are word-aligned, so strcpy () will be faster. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(((TREE_CODE (TYPE) == ARRAY_TYPE) \
&& (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
&& ((ALIGN) < BITS_PER_WORD)) \
? (BITS_PER_WORD) : (ALIGN))
/* In CR16 strings are word-aligne; strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(CONSTANT, ALIGN) \
(((TREE_CODE (CONSTANT) == STRING_CST) && ((ALIGN) < BITS_PER_WORD)) \
? (BITS_PER_WORD) : (ALIGN))
#define STRICT_ALIGNMENT 0
#define PCC_BITFIELD_TYPE_MATTERS 1
/* Layout of source language data types. */
#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE "long unsigned int"
#define PTRDIFF_TYPE "long int"
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
/* By default, the C++ compiler will use the lowest bit of the pointer
to function to indicate a pointer-to-member-function points to a
virtual member function. However, in CR architecture FUNCTION_BOUNDARY
indicates function addresses are always even, but function pointers can be
odd (after right-shifting them when loading them into a register), and the
default doesn't work. In that case, the lowest bit of the delta
field will be used (the remainder of the field is shifted to the left). */
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
values must be in memory. */
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Register usage. */
/* First 32-bit register is R12. */
#define CR16_FIRST_DWORD_REGISTER 12
#define FIRST_PSEUDO_REGISTER 16
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the CR16, only the stack pointer (r15) is such. */
#define FIXED_REGISTERS \
{ \
/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* r11 r12 r13 ra sp. */ \
0, 0, 0, 0, 1 \
}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
On the CR16, calls clobbers r0-r6 (scratch registers),
ra (the return address) and sp (the stack pointer). */
#define CALL_USED_REGISTERS \
{ \
/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \
1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
/* r11 r12 r13 ra sp. */ \
0, 0, 0, 1, 1 \
}
/* Returns 1 if the register is longer than word size, 0 otherwise. */
#define LONG_REG_P(REGNO) \
(HARD_REGNO_NREGS (REGNO, \
GET_MODE_WIDER_MODE (smallest_mode_for_size \
(BITS_PER_WORD, MODE_INT))) == 1)
#define HARD_REGNO_NREGS(REGNO, MODE) \
((REGNO >= CR16_FIRST_DWORD_REGISTER) \
? ((GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD)\
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Nonzero if it is permissible to store a value of mode @var{mode} in hard
register number @var{regno} (or in several registers starting with that
one). On the CR16 architecture, all registers can hold all modes,
except that double precision floats (and double ints) must fall on
even-register boundaries. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) cr16_hard_regno_mode_ok (REGNO, MODE)
#define NOTICE_UPDATE_CC(EXP, INSN) \
notice_update_cc ((EXP))
/* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be call-clobbered
Check if sizes are same and then check if it is possible to rename. */
#define HARD_REGNO_RENAME_OK(SRC, DEST) \
(!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST)))
/* Exception handling stuff. */
/*To ensure correct dwarf unwinding. */
#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse")))
#define gen_rtx_RA gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM)
/* Use (r8,r7) and (r10,r9) to pass exception handling information. */
#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM)
#define DWARF2_UNWIND_INFO 1
/* (r5,r4) holds a stack adjustment for returning to a handler. */
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 4)
#define EH_RETURN_HANDLER_RTX \
gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -4))
#define INCOMING_RETURN_ADDR_RTX gen_rtx_RA
#define DWARF_FRAME_RETURN_COLUMN \
DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM)
#define INCOMING_FRAME_SP_OFFSET 0
#define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
/* A C expression whose value is RTL representing the value of the return
address for the frame COUNT steps up from the current frame. */
#define RETURN_ADDR_RTX(COUNT, FRAME) \
(0 == COUNT) ? gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA) \
: const0_rtx
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
enum reg_class
{
NO_REGS,
SHORT_REGS,
LONG_REGS,
NOSP_REGS,
DOUBLE_BASE_REGS,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"SHORT_REGS", \
"LONG_REGS", \
"NOSP_REGS", \
"DOUBLE_BASE_REGS", \
"GENERAL_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{0x00000000}, /* NO_REGS */ \
{0x00000FFF}, /* SHORT_REGS : 0 - 11 */ \
{0x0000F000}, /* LONG_REGS : 12 - 15 */ \
{0x00007FFF}, /* NOSP_REGS : 0 - 14 */ \
{0x0000F555}, /* DOUBLE_BASE_REGS : 2,4,6,8,10 */ \
{0x0000FFFF}, /* GENERAL_REGS : 0 - 15 */ \
{0x0000FFFF} /* ALL_REGS : 0 - 15 */ \
}
#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
#define REGNO_REG_CLASS(REGNO) cr16_regno_reg_class (REGNO)
#define BASE_REG_CLASS GENERAL_REGS
#define MODE_BASE_REG_CLASS(MODE) \
(GET_MODE_SIZE (MODE) <= 4 ? (BASE_REG_CLASS) : (DOUBLE_BASE_REGS))
#define INDEX_REG_CLASS LONG_REGS
#define CR16_REGNO_OK_FOR_BASE_P(REGNO) \
(((REGNO) < FIRST_PSEUDO_REGISTER) \
|| (reg_renumber && ((unsigned) reg_renumber[REGNO] \
< FIRST_PSEUDO_REGISTER)))
/* Use even-numbered reg for 64-bit accesses. */
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
(CR16_REGNO_OK_FOR_BASE_P(REGNO) && \
((GET_MODE_SIZE (MODE) > 4 && \
(REGNO) < CR16_FIRST_DWORD_REGISTER) \
? (0 == ((REGNO) & 1)) \
: 1))
/* TODO: For now lets not support index addressing mode. */
#define REGNO_OK_FOR_INDEX_P(REGNO) \
(((REGNO >= CR16_FIRST_DWORD_REGISTER) \
&& ((REGNO) < FIRST_PSEUDO_REGISTER)) \
|| (reg_renumber \
&& (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER) \
&& ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \
)
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
/* The maximum number of consecutive registers of class CLASS needed to
hold a value of mode MODE.
On the CompactRISC architecture, the size of MODE in words.
The size of MODE in double words for the class LONG_REGS.
The following check assumes if the class is not LONG_REGS, then
all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are
short. We may have to check if this can cause any degradation in
performance. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
(CLASS == LONG_REGS \
? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Macros to check the range of integers . These macros were used across
the port, majorly in constraints.md, predicates.md files. */
#define SIGNED_INT_FITS_N_BITS(imm, N) \
((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1))) \
&& ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0)
#define UNSIGNED_INT_FITS_N_BITS(imm, N) \
(((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0)
#define IN_RANGE_P(VALUE, LOW, HIGH) \
((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \
&& (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
#define IN_RAN(VALUE, LOW, HIGH) \
(((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \
&& (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0)
/* This check is for sbit/cbit instruction. */
#define OK_FOR_Z(OP) \
((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
&& GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
&& GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
/* Stack layout and calling conventions. */
#define STACK_GROWS_DOWNWARD
#define STARTING_FRAME_OFFSET 0
#define STACK_POINTER_REGNUM 15
#define FRAME_POINTER_REGNUM 13
#define ARG_POINTER_REGNUM 12
#define STATIC_CHAIN_REGNUM 1
#define RETURN_ADDRESS_REGNUM 14
#define FIRST_PARM_OFFSET(FNDECL) 0
#define ELIMINABLE_REGS \
{ \
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
do \
{ \
(OFFSET) = cr16_initial_elimination_offset ((FROM), (TO)); \
} \
while (0)
/* Passing function arguments. */
#define ACCUMULATE_OUTGOING_ARGS 0
#define PUSH_ARGS 1
#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
#ifndef CUMULATIVE_ARGS
struct cumulative_args
{
int ints;
int last_parm_in_reg;
};
#define CUMULATIVE_ARGS struct cumulative_args
#endif
/* On the CR16 architecture, Varargs routines should receive their parameters
on the stack. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
#define FUNCTION_ARG_REGNO_P(REGNO) cr16_function_arg_regno_p (REGNO)
/* Generating code for profiling - NOT IMPLEMENTED. */
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO) \
{ \
sorry ("profiler support for CR16"); \
}
/* Trampolines for nested functions - NOT SUPPORTED. */
#define TRAMPOLINE_SIZE 16
/* ADDRESSING MODES. */
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST \
|| GET_CODE (X) == CONST_INT)
#define MAX_REGS_PER_ADDRESS 2
#define HAVE_POST_INCREMENT 0
#define HAVE_POST_DECREMENT 0
#define HAVE_POST_MODIFY_DISP 0
#define HAVE_POST_MODIFY_REG 0
#ifdef REG_OK_STRICT
#define CR16_REG_OK_FOR_BASE_P(X) CR16_REGNO_OK_FOR_BASE_P (REGNO (X))
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE)
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#else /* not REG_OK_STRICT. */
#define CR16_REG_OK_FOR_BASE_P(X) 1
#define REG_MODE_OK_FOR_BASE_P(X, MODE) 1
#define REG_OK_FOR_INDEX_P(X) 1
#endif /* not REG_OK_STRICT. */
/* Go to LABEL if ADDR (a legitimate address expression) has
an effect that depends on the machine mode it is used for. */
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
/* Assume best case (branch predicted). */
#define BRANCH_COST(speed_p, predictable_p) 2
#define SLOW_BYTE_ACCESS 1
/* It is as good or better to call a constant function address than to
call an address kept in a register. */
#define NO_FUNCTION_CSE
/* Dividing the output into sections. */
#define TEXT_SECTION_ASM_OP "\t.section\t.text"
#define DATA_SECTION_ASM_OP "\t.section\t.data"
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
/* Position independent code (PIC). */
/* NEAR_PIC for -fpic option. */
#define NEAR_PIC 1
/* FAR_PIC for -fPIC option. */
#define FAR_PIC 2
#define PIC_OFFSET_TABLE_REGNUM 12
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
/* Assembler format. */
/* Character to start a comment. */
#define ASM_COMMENT_START "#"
#define GLOBAL_ASM_OP "\t.globl\t"
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX "_"
#undef ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
do \
{ \
const char *rn = XSTR (SYMBOL, 0); \
assemble_name (STREAM, rn); \
if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
{ \
fprintf ((STREAM), "@c"); \
} \
} \
while (0)
#undef ASM_APP_ON
#define ASM_APP_ON "#APP\n"
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
/* Switch into a generic section. */
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
#undef INIT_SECTION_ASM_OP
#define INIT_SECTION_ASM_OP "\t.section\t.init"
#undef FINI_SECTION_ASM_OP
#define FINI_SECTION_ASM_OP "\t.section\t.fini"
/* Instruction output. */
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp" \
}
/* Output of dispatch tables. */
/* Revisit. No PC relative case as label expressions are not
properly supported in binutils else we could have done this:
#define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0). */
#define CASE_VECTOR_PC_RELATIVE 0
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
((GET_MODE (BODY) == QImode) \
? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n", \
VALUE, REL) \
: fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n", \
VALUE, REL))
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE))
/* Alignment in assembler file. */
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
/* Miscellaneous parameters. */
#define CASE_VECTOR_MODE Pmode
#define MOVE_MAX 4
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define STORE_FLAG_VALUE 1
#define Pmode SImode
#define FUNCTION_MODE QImode
/* Define this boolean macro(s) to indicate whether or not your architecture
has (un)conditional branches that can span all of memory. It is used in
conjunction with an optimization that partitions hot and cold basic blocks
into separate sections of the executable.
CR16 contains branch instructions that span whole address space. */
#define HAS_LONG_COND_BRANCH 1
#define HAS_LONG_UNCOND_BRANCH 1
#endif /* End of GCC_CR16_H. */

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51
gcc/config/cr16/cr16.opt Normal file
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@ -0,0 +1,51 @@
; Options for the National Semiconductor CR16 port of the compiler.
; Copyright (C) 2012 Free Software Foundation, Inc.
; Contributed by KPIT Cummins Infosystems Limited.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
msim
Target
-msim Use simulator runtime
mbit-ops
Target Report Mask(BIT_OPS)
Generate SBIT, CBIT instructions
mmac
Target Report Mask(MAC)
Support multiply accumulate instructions
mdebug-addr
Target RejectNegative Var(TARGET_DEBUG_ADDR) Undocumented
mdata-model=
Target RejectNegative JoinedOrMissing Var(cr16_data_model)
Treat data references as near, far or medium. medium is default
mcr16c
Target RejectNegative Mask(CR16C)
Generate code for CR16C architecture
mcr16cplus
Target RejectNegative InverseMask(CR16C,CR16CP)
Generate code for CR16C+ architecture (Default)
mint32
Target RejectNegative Mask(INT32)
Treat integers as 32-bit.

225
gcc/config/cr16/predicates.md Normal file
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@ -0,0 +1,225 @@
;; Predicates of machine description for CR16.
;; Copyright (C) 2012 Free Software Foundation, Inc.
;; Contributed by KPIT Cummins Infosystems Limited.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Predicates
;; Predicates for sbit/cbit instructions
;; bit operand used for the generation of bit insn generation
(define_predicate "bit_operand"
(match_code "mem")
{
return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
})
;; Unsigned 4-bits constant int or double value.
(define_predicate "u4bits_operand"
(match_code "const_int,const_double")
{
if (GET_CODE (op) == CONST_DOUBLE)
return cr16_const_double_ok (op);
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
})
;; Operand is a constant integer where
;; only one bit is set to 1.
(define_predicate "one_bit_operand"
(match_code "const_int")
{
unsigned int val;
val = INTVAL (op);
if (mode == QImode)
val &= 0xff;
else if (mode == HImode)
val &= 0xffff;
else
gcc_unreachable();
if (val != 0)
return (val & (val - 1)) == 0; /* true if only one bit is set. */
else
return 0;
})
;; Operand is a constant integer where
;; only one bit is set to 0.
(define_predicate "rev_one_bit_operand"
(match_code "const_int")
{
unsigned int val;
val = ~INTVAL (op); /* Invert and use. */
if (mode == QImode)
val &= 0xff;
else if (mode == HImode)
val &= 0xffff;
else
gcc_unreachable();
if (val != 0)
return (val & (val - 1)) == 0; /* true if only one bit is set. */
else
return 0;
})
;; Predicates for shift instructions
;; Immediate operand predicate for count in shift operations.
;; Immediate shall be 3-bits in case operand to be operated on
;; is a qi mode operand.
(define_predicate "shift_qi_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 3)) ? 1 : 0;
})
;; Immediate shall be 4-bits in case operand to be operated on
;; is a hi mode operand.
(define_predicate "shift_hi_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
})
;; Immediate shall be 3-bits in case operand to be operated on
;; is a si mode operand.
(define_predicate "shift_si_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 5)) ? 1 : 0;
})
;; Predicates for jump/call instructions
;; Jump immediate cannot be more than 24-bits
(define_predicate "jump_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
})
;; Call immediate cannot be more than 24-bits
(define_predicate "call_imm_operand"
(match_operand 0 "immediate_operand")
{
if (GET_CODE (op) != CONST_INT) return 1;
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
})
;; Operand is register or 4-bit immediate operand
(define_predicate "reg_or_u4bits_operand"
(ior (match_operand 0 "u4bits_operand")
(match_operand 0 "register_operand")))
;; Operand is a register or symbol reference
(define_predicate "reg_or_sym_operand"
(ior (match_code "symbol_ref")
(match_operand 0 "register_operand")))
;; Operand is a non stack pointer register
(define_predicate "nosp_reg_operand"
(and (match_operand 0 "register_operand")
(match_test "REGNO (op) != SP_REGNUM")))
(define_predicate "hard_reg_operand"
(and (match_operand 0 "register_operand")
(match_test "REGNO (op) <= 15")))
;; Operand is a memory reference and
;; not a push operand.
(define_predicate "store_operand"
(and (match_operand 0 "memory_operand")
(not (match_operand 0 "push_operand"))))
;; Helper predicate
(define_predicate "reg_or_int_operand"
(ior (match_code "const_int")
(match_operand 0 "register_operand")))
;;
;;
;; Atithmetic/logical predicates
;; QI Helper
(define_predicate "arith_qi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 15) && ((INTVAL (op) != 9)
|| (INTVAL (op) != 11))) ? 1 : 0 ;
})
;;QI Reg, subreg(reg) or const_int.
(define_predicate "reg_qi_int_operand"
(ior (match_operand 0 "arith_qi_operand")
(match_operand 0 "register_operand")))
;; HI Helper
(define_predicate "arith_hi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), -32768, 32768) ) ? 1 : 0 ;
})
;;HI Reg, subreg(reg) or const_int.
(define_predicate "reg_hi_int_operand"
(ior (match_operand 0 "arith_hi_operand")
(match_operand 0 "register_operand")))
;;SI Reg, subreg(reg) or const_int.
(define_predicate "reg_si_int_operand"
(ior (match_operand 0 "const_int_operand")
(match_operand 0 "register_operand")))
;;
;; Shift predicates
;; QI Helper
(define_predicate "shift_qi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 7) ) ? 1 : 0;
})
;;QI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_qi_int_operand"
(ior (match_operand 0 "shift_qi_operand")
(match_operand 0 "register_operand")))
;; HI Helper
(define_predicate "shift_hi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 15) ) ? 1 : 0 ;
})
;;HI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_hi_int_operand"
(ior (match_operand 0 "shift_hi_operand")
(match_operand 0 "register_operand")))
;; SI Helper
(define_predicate "shift_si_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 31) ) ? 1 : 0;
})
;;SI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_si_int_operand"
(ior (match_operand 0 "shift_si_operand")
(match_operand 0 "register_operand")))

25
gcc/config/cr16/t-cr16 Normal file
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@ -0,0 +1,25 @@
# CR16 Target Makefile
# Copyright (C) 2012 Free Software Foundation, Inc.
# Contributed by KPIT Cummins Infosystems Limited.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
MULTILIB_OPTIONS = fPIC mint32
MULTILIB_DIRNAMES = far-pic int32
MULTILIB_MATCHES =
MULTILIB_EXTRA_OPTS = mcr16cplus mdata-model=far

2
gcc/doc/extend.texi
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@ -2723,7 +2723,7 @@ This attribute is ignored for R8C target.
@item interrupt
@cindex interrupt handler functions
Use this attribute on the ARM, AVR, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
Use this attribute on the ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
RL78, RX and Xstormy16 ports to indicate that the specified function is an
interrupt handler. The compiler will generate function entry and exit
sequences suitable for use in an interrupt handler when this attribute

23
gcc/doc/install.texi
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@ -3269,6 +3269,29 @@ See ``Blackfin Options'' in the main manual
More information, and a version of binutils with support for this processor,
is available at @uref{http://blackfin.uclinux.org}
@html
<hr />
@end html
@heading @anchor{cr16}CR16
The CR16 CompactRISC architecture is a 16-bit architecture. This architecture is
used in embedded applications.
@ifnothtml
@xref{CR16 Options,, CR16 Options, gcc, Using and Porting the GNU Compiler
Collection (GCC)},
@end ifnothtml
@ifhtml
See ``CR16 Options'' in the main manual for a list of CR16-specific options.
@end ifhtml
Use @samp{configure --target=cr16-elf --enable-languages=c,c++} to configure
GCC@ for building a CR16 elf cross-compiler.
Use @samp{configure --target=cr16-uclinux --enable-languages=c,c++} to configure
GCC@ for building a CR16 uclinux cross-compiler.
@html
<hr />
@end html

47
gcc/doc/invoke.texi
View File

@ -524,6 +524,12 @@ Objective-C and Objective-C++ Dialects}.
-melf -maout -melinux -mlinux -sim -sim2 @gol
-mmul-bug-workaround -mno-mul-bug-workaround}
@emph{CR16 Options}
@gccoptlist{-mmac @gol
-mcr16cplus -mcr16c @gol
-msim -mint32 -mbit-ops
-mdata-model=@var{model}}
@emph{Darwin Options}
@gccoptlist{-all_load -allowable_client -arch -arch_errors_fatal @gol
-arch_only -bind_at_load -bundle -bundle_loader @gol
@ -10307,6 +10313,7 @@ platform.
* Blackfin Options::
* C6X Options::
* CRIS Options::
* CR16 Options::
* Darwin Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
@ -11634,6 +11641,46 @@ Like @option{-sim}, but pass linker options to locate initialized data at
0x40000000 and zero-initialized data at 0x80000000.
@end table
@node CR16 Options
@subsection CR16 Options
@cindex CR16 Options
These options are defined specifically for the CR16 ports.
@table @gcctabopt
@item -mmac
@opindex mmac
Enable the use of multiply-accumulate instructions. Disabled by default.
@item -mcr16cplus
@itemx -mcr16c
@opindex mcr16cplus
@opindex mcr16c
Generate code for CR16C or CR16C+ architecture. CR16C+ architecture
is default.
@item -msim
@opindex msim
Links the library libsim.a which is in compatible with simulator. Applicable
to elf compiler only.
@item -mint32
@opindex mint32
Choose integer type as 32-bit wide.
@item -mbit-ops
@opindex mbit-ops
Generates sbit/cbit instructions for bit manipulations.
@item -mdata-model=@var{model}
@opindex mdata-model
Choose a data model. The choices for @var{model} are @samp{near},
@samp{far} or @samp{medium}. @samp{medium} is default.
However, @samp{far} is not valid when -mcr16c option is chosen as
CR16C architecture does not support far data model.
@end table
@node Darwin Options
@subsection Darwin Options
@cindex Darwin options

34
gcc/doc/md.texi
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@ -1843,6 +1843,40 @@ Matches control register values to switch fp mode, which are encapsulated in
@code{UNSPEC_FP_MODE}.
@end table
@item CR16 Architecture---@file{config/cr16/cr16.h}
@table @code
@item b
Registers from r0 to r14 (registers without stack pointer)
@item t
Register from r0 to r11 (all 16-bit registers)
@item p
Register from r12 to r15 (all 32-bit registers)
@item I
Signed constant that fits in 4 bits
@item J
Signed constant that fits in 5 bits
@item K
Signed constant that fits in 6 bits
@item L
Unsigned constant that fits in 4 bits
@item M
Signed constant that fits in 32 bits
@item N
Check for 64 bits wide constants for add/sub instructions
@item G
Floating point constant that is legal for store immediate
@end table
@item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
@table @code
@item a

14
libgcc/ChangeLog
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@ -1,3 +1,17 @@
2012-02-02 Sumanth G <sumanth.gundapaneni@kpitcummins.com>
Jayant R Sonar <jayant.sonar@kpitcummins.com>
* config.host: Add National Semiconductor CR16 target (cr16-*-*).
* config/cr16/crti.S: New file.
* config/cr16/crtlibid.S: New file.
* config/cr16/crtn.S: New file.
* config/cr16/lib1funcs.S: New file.
* config/cr16/t-cr16: New file.
* config/cr16/t-crtlibid: New file.
* config/cr16/unwind-dw2.h: New file.
* config/cr16/unwind-cr16.c: New file.
* config/cr16/divmodhi3.c: New file.
2012-01-25 Alan Modra <amodra@gmail.com>
* config/rs6000/t-linux64: Delete. Move..

6
libgcc/config.host
View File

@ -98,6 +98,8 @@ avr-*-*)
bfin*-*)
cpu_type=bfin
;;
cr16-*-*)
;;
fido-*-*)
cpu_type=m68k
;;
@ -415,6 +417,10 @@ bfin*-*)
tmake_file="$tmake_file bfin/t-bfin t-fdpbit"
extra_parts="crtbegin.o crtend.o crti.o crtn.o"
;;
cr16-*-elf)
tmake_file="${tmake_file} cr16/t-cr16 cr16/t-crtlibid t-fdpbit"
extra_parts="$extra_parts crti.o crtn.o crtlibid.o"
;;
crisv32-*-elf)
tmake_file="$tmake_file cris/t-cris t-fdpbit"
;;

54
libgcc/config/cr16/crti.S Normal file
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@ -0,0 +1,54 @@
# Specialized code needed to support construction and destruction of
# file-scope objects in C++ and Java code, and to support exception handling.
# Copyright (C) 2012 Free Software Foundation, Inc.
# Contributed by KPIT Cummins Infosystems Limited.
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
/* This file just supplies function prologues for the .init and .fini
sections. It is linked in before crtbegin.o. */
.ident "GNU C crti.o"
.section .init
.globl __init
.type __init,@function
__init:
#if defined (__ID_SHARED_LIB__)
push $2, r12, ra
movd $__current_shared_library_r12_offset_, (r1,r0)
loadd [r12]0(r1,r0), (r12)
#else
push ra
#endif
.section .fini
.globl __fini
.type __fini,@function
__fini:
#if defined (__ID_SHARED_LIB__)
push $2, r12, ra
movd $__current_shared_library_r12_offset_, (r1,r0)
loadd [r12]0(r1,r0), (r12)
#else
push ra
#endif

28
libgcc/config/cr16/crtlibid.S Normal file
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# Provide a weak definition of the library ID, for the benefit of certain
# configure scripts.
# Copyright (C) 2012 Free Software Foundation, Inc.
# Contributed by KPIT Cummins Infosystems Limited.
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
.ident "GNU C crtlibid.o"
.weak __current_shared_library_r12_offset_
.set __current_shared_library_r12_offset_, 0

44
libgcc/config/cr16/crtn.S Normal file
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# Specialized code needed to support construction and destruction of
# file-scope objects in C++ and Java code, and to support exception handling.
# Copyright (C) 2012 Free Software Foundation, Inc.
# Contributed by KPIT Cummins Infosystems Limited.
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
/* This file supplies function epilogues for the .init and .fini sections.
It is linked in after all other files. */
.ident "GNU C crtn.o"
.section .init
#if defined (__ID_SHARED_LIB__)
popret $2, r12, ra
#else
popret ra
#endif
.section .fini
#if defined (__ID_SHARED_LIB__)
popret $2, r12, ra
#else
popret ra
#endif

115
libgcc/config/cr16/divmodhi3.c Normal file
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/* Libgcc Target specific implementation - Emulating div and mod.
Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Limited.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Emulate the division and modulus operation. */
unsigned short
udivmodhi4 (unsigned short num, unsigned short den, short modwanted)
{
unsigned short bit = 1;
unsigned short res = 0;
while (den < num && bit && !(den & (1 << 15)))
{
den <<= 1;
bit <<= 1;
}
while (bit)
{
if (num >= den)
{
num -= den;
res |= bit;
}
bit >>= 1;
den >>= 1;
}
if (modwanted)
return num;
return res;
}
short
__divhi3 (short a, short b)
{
short neg = 0;
short res;
if (a < 0)
{
a = -a;
neg = !neg;
}
if (b < 0)
{
b = -b;
neg = !neg;
}
res = udivmodhi4 (a, b, 0);
if (neg)
res = -res;
return res;
}
short
__modhi3 (short a, short b)
{
short neg = 0;
short res;
if (a < 0)
{
a = -a;
neg = 1;
}
if (b < 0)
b = -b;
res = udivmodhi4 (a, b, 1);
if (neg)
res = -res;
return res;
}
short
__udivhi3 (short a, short b)
{
return udivmodhi4 (a, b, 0);
}
short
__umodhi3 (short a, short b)
{
return udivmodhi4 (a, b, 1);
}

563
libgcc/config/cr16/lib1funcs.S Normal file
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/* Libgcc Target specific implementation.
Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Limited.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef L_mulsi3
.text
.align 4
.globl ___mulsi3
___mulsi3:
movw r4,r0
movw r2,r1
/* Extended multiplication between the 2 lower words */
muluw r1,(r1,r0)
/* Multiply the lower word of each parameter */
mulw r2,r5
/* With the higher word of the other */
mulw r3,r4
/* Add products to the higher part of the final result */
addw r4,r1
addw r5,r1
jump (ra)
#endif
#ifdef L_divdi3
.text
.align 4
.globl ___divdi3
___divdi3:
push $4, r7, ra
/* Param #1 Long Long low bit first */
loadd 12(sp), (r1, r0)
loadd 16(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 20(sp), (r5, r4)
loadd 24(sp), (r7, r6)
/* Set neg to 0 */
movw $0, r10
subd $16, (sp)
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L4
/* Invert param1 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
xorw $1, r10 /* Invert neg */
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L4: stord (r1, r0), 0(sp)
stord (r3, r2), 4(sp)
/* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L5
/* Invert param2 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
xorw $1, r10 /* Invert neg */
bcc L5 /* If no carry occurred go to L5 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L5: stord (r5, r4), 8(sp)
stord (r7, r6), 12(sp)
movw $0, r2
/* Call udivmoddi3 */
#ifdef __PIC__
loadd ___udivmoddi3@cGOT(r12), (r1,r0)
jal (r1,r0)
#else
bal (ra), ___udivmoddi3
#endif
/* If (neg) */
addd $16, (sp)
cmpw $0, r10 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
xord (r9, r8), (r1, r0) /* Xor low bits of ures with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of ures with temp */
addd $1, (r1, r0) /* Add 1 to low bits of ures */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of ures */
Lexit__:
# ifdef __ID_SHARED_LIB__
pop $2, r12
# endif
popret $4, r7, ra
#endif
#ifdef L_lshrdi3
.text
.align 4
.globl ___lshrdi3
___lshrdi3:
push $3, r7
/* Load parameters from stack in this order */
movw r2, r6 /* Number of shifts */
loadd 6(sp), (r1, r0) /* Low bits */
loadd 10(sp), (r3, r2)/* High bits */
xorw $-1, r6 /* Invert number of shifts */
addw $1, r6 /* Add 1 by number of shifts */
movw r6, r7 /* Copy number of shifts */
tbit $15, r6 /* Test if number is negative */
bfs L2 /* If negative jump to L2 */
movd (r1, r0), (r9, r8) /* Copy low bits */
subw $32, r7 /* Calc how many bits will overflow */
/* Shift the temp low bit to the right to see the overflowing bits */
lshd r7, (r9, r8)
cmpw $32, r6 /* If number of shifts is higher than 31 */
blt L1 /* Shift by moving */
lshd r6, (r3, r2) /* Shift high bits */
lshd r6, (r1, r0) /* Shift low bits */
addd (r9, r8), (r3, r2) /* Add overflow to the high bits */
popret $3, r7 /* Return */
L1: movd $0, (r1, r0) /* Reset low bit */
movd (r9, r8), (r3, r2) /* Add the overflow from the low bit */
popret $3, r7 /* Return */
L2: movd (r3, r2), (r9, r8) /* Copy high bits */
addw $32, r7 /* Calc how many bits will overflow */
/* Shift the temp low bit to the left to see the overflowing bits */
lshd r7, (r9, r8)
cmpw $-32, r6 /* If number of shifts is lower than -31 */
bgt L3 /* Shift by moving */
lshd r6, (r1, r0) /* Shift low bits */
lshd r6, (r3, r2) /* Shift high bits */
addd (r9, r8), (r1, r0) /* Add overflow to the low bits */
popret $3, r7 /* Return */
L3: movd $0, (r3, r2) /* Reset the high bit */
movd (r9, r8), (r1, r0) /* Add the overflow from the high bit */
popret $3, r7 /* Return */
#endif
#ifdef L_moddi3
.text
.align 4
.globl ___moddi3
___moddi3:
push $4, r7, ra
/* Param #1 Long Long low bit first */
loadd 12(sp), (r1, r0)
loadd 16(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 20(sp), (r5, r4)
loadd 24(sp), (r7, r6)
subd $18, (sp)
/* Set neg to 0 */
storw $0, 16(sp)
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L4
/* Invert param1 and neg */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
storw $1, 16(sp)
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L4: stord (r1, r0), 0(sp)
stord (r3, r2), 4(sp)
/* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L5
/* Invert param2 and neg */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
bcc L5 /* If no carry occurred go to L5 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L5: stord (r5, r4), 8(sp)
stord (r7, r6), 12(sp)
movw $1, r2
/* Call udivmoddi3 */
#ifdef __PIC__
loadd ___udivmoddi3@cGOT(r12), (r1,r0)
jal (r1,r0)
#else
bal (ra), ___udivmoddi3
#endif
/* If (neg) */
loadw 16(sp), r10 /* Load neg from stack */
addd $18, (sp)
cmpw $0, r10 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
xord (r9, r8), (r1, r0) /* Xor low bits of ures with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of ures with temp */
addd $1, (r1, r0) /* Add 1 to low bits of ures */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of ures */
Lexit__:
# ifdef __ID_SHARED_LIB__
pop $2, r12
# endif
popret $4, r7, ra
#endif
#ifdef L_muldi3
.text
.align 4
.globl ___muldi3
___muldi3:
push $2, r13
push $7, r7
/* Param #1 Long Long low bit first */
loadd 18(sp), (r1, r0)
loadd 22(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 26(sp), (r5, r4)
loadd 30(sp), (r7, r6)
/* Clear r13, r12 */
movd $0, (r12)
movd $0, (r13)
/* Set neg */
movw $0, r10
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L1
/* Invert param1 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
xorw $1, r10 /* Invert neg */
bcc L1 /* If no carry occurred go to L1 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L1: /* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L2
/* Invert param2 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
xorw $1, r10 /* Invert neg */
bcc L2 /* If no carry occurred go to L2 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L2: storw r10, 18(sp) /* Store neg to stack so we can use r10 */
/* B*D */
/* Bl*Dl */
macuw r0, r4, (r12) /* Multiply r0 and r4 and add to r12 */
/* Bh*Dl */
movd $0, (r9, r8) /* Clear r9, r8 */
macuw r1, r4, (r9, r8) /* Multiply Bh*Dl and add result to (r9, r8) */
movw r9, r10 /* Shift left: r9 to r10 */
lshd $16, (r9, r8) /* Shift left: r8 to r9 */
movw $0, r11 /* Clear r11 */
addd (r9, r8), (r12) /* Add (r9, r8) to r12 */
bcc L3 /* If no carry occurred go to L3 */
addd $1, (r13) /* If carry occurred add 1 to r13 */
L3: addd (r11, r10), (r13) /* Add (r11, r10) to r13 */
/* Bl*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r5, (r9, r8) /* Multiply r0 and r5 and stor in (r9, r8) */
movw r9, r10 /* Shift left: r9 to r10 */
lshd $16, (r9, r8) /* Shift left: r8 to r9 */
addd (r9, r8), (r12) /* Add (r9, r8) to r12 */
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r13) /* If carry occurred add 1 to r13 */
L4: addd (r11, r10), (r13) /* Add (r11, r10) to r13 */
/* Bh*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r1, r5, (r9, r8) /* Multiply r1 and r5 and add to r13 */
addd (r9, r8), (r13) /* Add (r9, r8) to result */
/* A*D */
/* Al*Dl */
movd $0, (r11, r10) /* Clear (r11, r10) */
macuw r2, r4, (r11, r10)/* Multiply r2 and r4 and add to (r11, r10) */
addd (r13), (r11, r10) /* Copy r13 to (r11, r10) */
/* Al*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r2, r5, (r9, r8) /* Multiply r2 and r5 and add to (r9, r8) */
addw r8, r11 /* Add r8 to r11 */
/* Ah*Dl */
muluw r3, (r5, r4) /* Multiply r3 and r4 and stor in (r5, r4) */
addw r4, r11 /* Add r4 to r11 */
/* B*C */
/* Bl*Cl */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r6, (r9, r8) /* Multiply r0 and r6 and add to (r9, r8) */
addd (r9, r8), (r11, r10)/* Add (r9, r8) to result */
/* Bl*Ch */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r7, (r9, r8) /* Multiply r0 and r7 and add to (r9, r8) */
addw r8, r11 /* Add r8 to r11 */
loadw 18(sp), r8 /* Load neg from stack */
/* Bh*Cl */
muluw r1, (r7, r6) /* Multiply r1 and r6 and stor in (r7, r6) */
addw r6, r11 /* Add r6 to r11 */
E1: movd (r11, r10), (r3, r2)
movd (r12), (r1, r0)
/* If (neg) */
cmpw $0, r8 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of result with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of result with temp */
addd $1, (r1, r0) /* Add 1 to low bits of result */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of result */
Lexit__:
pop $7, r7
popret $2, r13
#endif
#ifdef L_negdi2
.text
.align 4
.globl ___negdi2
___negdi2:
/* Load parameter from the registers in this order */
loadd 0(sp), (r1, r0)
loadd 4(sp), (r3, r2)
movd $-1, (r6, r5) /* Set temp to FFFFFFFF */
xord (r6, r5), (r1, r0) /* Xor low bits with temp */
xord (r6, r5), (r3, r2) /* Xor high bits with temp */
addd $1, (r1, r0) /* Add one */
jcc (ra)
addd $1, (r3, r2) /* Add the carry to the high bits */
jump (ra)
#endif
#ifdef L_udivdi3
.text
.align 4
.globl ___udivdi3
___udivdi3:
movw $0, r2
br ___udivmoddi3
#endif
#ifdef L_udivmoddi3
.text
.align 4
.globl ___udivmoddi3
___udivmoddi3:
push $2, r13
push $7, r7
/* Param #1 Long Long low bit first */
loadd 18(sp), (r1, r0)
storw r2, 18(sp) /* Store modulo on stack */
loadd 22(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 26(sp), (r5, r4)
loadd 30(sp), (r7, r6)
/* Set ures to 0 */
movd $0, (r13)
movd $0, (r12)
cmpd (r12), (r5, r4)
beq LE
L5: movd $1, (r9, r8) /* Store 1 in low bits from bit */
movd $0, (r11, r10) /* Store 0 in high bits from bit */
L6: /* While (den < num && (!den & (1LL<<63))) */
/* Compare high bits from param 1 and param 2 */
cmpd (r7, r6), (r3, r2)
bhi L10 /* If param 2 is greater go to L10 */
bne L8 /* If param 1 is greater go to L8 */
cmpd (r5, r4), (r1, r0) /* Compare low bits from param 1 and param 2 */
/* If param 2 is greater or the same go to L1 */
bhs L10
L8: /* Check if most significant bit of param 2 is set */
tbit $15, r7
bfs L10 /* If PSR is set go to L10 */
/* Shift bit */
lshd $1, (r11, r10) /* Shift left: high bits of bit */
/* Check if most significant bit of bit is set */
tbit $15, r9
lshd $1, (r9, r8) /* Shift left: low bits of bit */
bfs L28 /* If PSR is set go to L28 */
L9: /* Shift b */
lshd $1, (r7, r6) /* Shift left: high bits of param 2 */
/* Check if most significant bit of param 2 is set */
tbit $15, r5
lshd $1, (r5, r4) /* Shift left: low bits of param 2 */
bfc L6 /* If PSR is set go to L6 */
addw $1, r6 /* Add 1 to the highest bits of b */
br L6 /* Go to L6 */
L10: /* While (bit) */
cmpd $0, (r11, r10)
bne L11
cmpd $0, (r9, r8)
beq E1
L11: /* If (num >= den) */
cmpd (r3, r2), (r7, r6) /* Compare high bits of param 1 and param 2 */
blo L15 /* If param 1 lower than param 2 go to L15 */
bne L12 /* If not equal go to L12 */
cmpd (r1, r0), (r5, r4) /* Compare low bits of param 1 and param 2 */
blo L15 /* If param 1 lower than param 2 go to L15 */
L12: /* Ures |= bit */
ord (r11, r10), (r13)
ord (r9, r8), (r12)
/* Num -= den */
subd (r7, r6), (r3, r2) /* Subtract highest 32 bits from each other */
subd (r5, r4), (r1, r0) /* Subtract lowest 32 bits from each other */
bcc L15 /* If no carry occurred go to L15 */
subd $1, (r3, r2) /* Subtract the carry */
L15: /* Shift bit to the right */
lshd $-1, (r9, r8) /* Shift right: low bits of bit */
/* Check if least significant bit of high bits is set */
tbit $0, r10
lshd $-1, (r11, r10) /* Shift right: high bits of bit */
bfs L18 /* If PSR is set go to L18 */
L17: /* Shift param#2 to the right */
lshd $-1, (r5, r4) /* Shift right: low bits of param 2 */
/* Check if least significant bit of high bits is set */
tbit $0, r6
lshd $-1, (r7, r6) /* Shift right: high bits of param 2 */
bfc L10 /* If PSR is not set go to L10 */
/* Or with 0x8000 to set most significant bit */
orw $32768, r5
br L10 /* Go to L10 */
L18: /* Or with 0x8000 to set most significant bit */
orw $32768, r9
br L17
L28: /* Left shift bit */
addw $1, r10 /* Add 1 to highest bits of bit */
br L9 /* Go to L9 */
LE: cmpd (r12), (r7, r6)
bne L5
excp dvz
br Lexit__
E1: loadw 18(sp), r4
cmpw $0, r4
bne Lexit__
/* Return result */
movd (r12), (r1, r0)
movd (r13), (r3, r2)
Lexit__:
pop $7, r7
popret $2, r13
#endif
#ifdef L_umoddi3
.text
.align 4
.globl ___umoddi3
___umoddi3:
movw $1, r2
br ___udivmoddi3
#endif

29
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# Makefile fragment for building LIBGCC for the Renesas CR16 target.
# Copyright (C) 2012 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
# the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
LIB1ASMSRC = cr16/lib1funcs.S
LIB1ASMFUNCS = _mulsi3 _lshrdi3 _muldi3 _divdi3 _udivdi3 _udivmoddi3 \
_umoddi3 _moddi3
LIB2ADD = $(srcdir)/config/cr16/divmodhi3.c \
$(srcdir)/udivmodsi4.c \
$(srcdir)/udivmod.c \
$(srcdir)/divmod.c
LIB2ADDEH = $(srcdir)/config/cr16/unwind-cr16.c

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# Makefile fragment for building LIBGCC for the Renesas CR16 target.
# Copyright (C) 2012 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
# the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Assemble startup files.
crtlibid.o: $(srcdir)/config/cr16/crtlibid.S
$(gcc_compile) -c -x assembler-with-cpp $<

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87
libgcc/config/cr16/unwind-dw2.h Normal file
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/* DWARF2 frame unwind data structure.
Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2009,
2010, 2011, 2012 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* A target can override (perhaps for backward compatibility) how
many dwarf2 columns are unwound. */
#ifndef DWARF_FRAME_REGISTERS
#define DWARF_FRAME_REGISTERS FIRST_PSEUDO_REGISTER
#endif
/* The result of interpreting the frame unwind info for a frame.
This is all symbolic at this point, as none of the values can
be resolved until the target pc is located. */
typedef struct
{
/* Each register save state can be described in terms of a CFA slot,
another register, or a location expression. */
struct frame_state_reg_info
{
struct {
union {
_Unwind_Word reg;
_Unwind_Sword offset;
const unsigned char *exp;
} loc;
enum {
REG_UNSAVED,
REG_SAVED_OFFSET,
REG_SAVED_REG,
REG_SAVED_EXP,
REG_SAVED_VAL_OFFSET,
REG_SAVED_VAL_EXP,
REG_UNDEFINED
} how;
} reg[DWARF_FRAME_REGISTERS+1];
/* Used to implement DW_CFA_remember_state. */
struct frame_state_reg_info *prev;
/* The CFA can be described in terms of a reg+offset or a
location expression. */
_Unwind_Sword cfa_offset;
_Unwind_Word cfa_reg;
const unsigned char *cfa_exp;
enum {
CFA_UNSET,
CFA_REG_OFFSET,
CFA_EXP
} cfa_how;
} regs;
/* The PC described by the current frame state. */
void *pc;
/* The information we care about from the CIE/FDE. */
_Unwind_Personality_Fn personality;
_Unwind_Sword data_align;
_Unwind_Word code_align;
_Unwind_Word retaddr_column;
unsigned char fde_encoding;
unsigned char lsda_encoding;
unsigned char saw_z;
unsigned char signal_frame;
void *eh_ptr;
} _Unwind_FrameState;