aarch64: Fix an ICE in aarch64_short_vector_p [PR95459]
In aarch64_short_vector_p, we are simply checking whether a type (and a mode) is a 64/128-bit short vector or not. This should not be affected by the value of TARGET_SVE. Simply leave later code to report an error if SVE is disabled. 2020-06-02 Felix Yang <felix.yang@huawei.com> gcc/ PR target/95459 * config/aarch64/aarch64.c (aarch64_short_vector_p): Leave later code to report an error if SVE is disabled. gcc/testsuite/ PR target/95459 * gcc.target/aarch64/mgeneral-regs_6.c: New test.
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@ -16800,7 +16800,8 @@ aarch64_short_vector_p (const_tree type,
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{
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/* Rely only on the type, not the mode, when processing SVE types. */
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if (type && aarch64_some_values_include_pst_objects_p (type))
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gcc_assert (aarch64_sve_mode_p (mode));
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/* Leave later code to report an error if SVE is disabled. */
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gcc_assert (!TARGET_SVE || aarch64_sve_mode_p (mode));
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else
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size = GET_MODE_SIZE (mode);
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}
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15
gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
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15
gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
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@ -0,0 +1,15 @@
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/* { dg-options "-O2 -march=armv8.2-a+sve" } */
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/* { dg-prune-output "compilation terminated" } */
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#include <arm_sve.h>
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#pragma GCC push_options
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#pragma GCC target "general-regs-only"
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svint8x2_t
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foo (svint8_t x0, svint8_t x1) /* { dg-error {'foo' requires the SVE ISA extension} } */
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{
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return svcreate2 (x0, x1); /* { dg-error {ACLE function 'svcreate2_s8' is incompatible with the use of '-mgeneral-regs-only'} } */
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}
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#pragma GCC pop_options
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