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Tune alignment for Intel Core i7 

* config/i386.h (TARGET_COREI7{_32,_64,}): New macros.
	(enum processor_type): Update comment.  Add entries for Core i7.
	* config/i386-c.c (ix86_target_macros_internal): Update.
	* config/i386.c (m_COREI7{_32,_64}): New macros.
	(m_GENERIC32, m_GENERIC64): Use generic tuning for Core i7.
	(processor_target_table): Tune alignment for Core i7.
	(ix86_option_override_internal): Use PROCESSOR_COREI7_*.

	* doc/invoke.texi: Document "corei7" option value.

Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>

From-SVN: r166177
This commit is contained in:
Bernd Schmidt 2010-11-02 12:34:02 +00:00 committed by Maxim Kuvyrkov
parent 2855d9d949
commit b2b0154307
5 changed files with 47 additions and 5 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2010-11-02 Bernd Schmidt <bernds@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
Tune alignment for Intel Core i7
* config/i386.h (TARGET_COREI7{_32,_64,}): New macros.
(enum processor_type): Update comment. Add entries for Core i7.
* config/i386-c.c (ix86_target_macros_internal): Update.
* config/i386.c (m_COREI7{_32,_64}): New macros.
(m_GENERIC32, m_GENERIC64): Use generic tuning for Core i7.
(processor_target_table): Tune alignment for Core i7.
(ix86_option_override_internal): Use PROCESSOR_COREI7_*.
* doc/invoke.texi: Document "corei7" option value.
2010-11-02 Bernd Schmidt <bernds@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
H.J. Lu <hjl.tools@gmail.com>

9
gcc/config/i386/i386-c.c
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@ -122,6 +122,11 @@ ix86_target_macros_internal (int isa_flag,
def_or_undef (parse_in, "__core2");
def_or_undef (parse_in, "__core2__");
break;
case PROCESSOR_COREI7_32:
case PROCESSOR_COREI7_64:
def_or_undef (parse_in, "__corei7");
def_or_undef (parse_in, "__corei7__");
break;
case PROCESSOR_ATOM:
def_or_undef (parse_in, "__atom");
def_or_undef (parse_in, "__atom__");
@ -197,6 +202,10 @@ ix86_target_macros_internal (int isa_flag,
case PROCESSOR_CORE2:
def_or_undef (parse_in, "__tune_core2__");
break;
case PROCESSOR_COREI7_32:
case PROCESSOR_COREI7_64:
def_or_undef (parse_in, "__tune_corei7__");
break;
case PROCESSOR_ATOM:
def_or_undef (parse_in, "__tune_atom__");
break;

17
gcc/config/i386/i386.c
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@ -1642,6 +1642,8 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
#define m_NOCONA (1<<PROCESSOR_NOCONA)
#define m_CORE2 (1<<PROCESSOR_CORE2)
#define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
#define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
#define m_ATOM (1<<PROCESSOR_ATOM)
#define m_GEODE (1<<PROCESSOR_GEODE)
@ -1654,8 +1656,8 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_BDVER1 (1<<PROCESSOR_BDVER1)
#define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1)
#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
#define m_GENERIC32 (1<<PROCESSOR_GENERIC32 | m_COREI7_32)
#define m_GENERIC64 (1<<PROCESSOR_GENERIC64 | m_COREI7_64)
/* Generic instruction choice should be common subset of supported CPUs
(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
@ -2461,6 +2463,10 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{&k8_cost, 16, 7, 16, 7, 16},
{&nocona_cost, 0, 0, 0, 0, 0},
{&core2_cost, 16, 10, 16, 10, 16},
/* Core i7 32-bit. */
{&generic32_cost, 16, 10, 16, 10, 16},
/* Core i7 64-bit. */
{&generic64_cost, 16, 10, 16, 10, 16},
{&generic32_cost, 16, 7, 16, 7, 16},
{&generic64_cost, 16, 10, 16, 10, 16},
{&amdfam10_cost, 32, 24, 32, 7, 32},
@ -3183,7 +3189,7 @@ ix86_option_override_internal (bool main_args_p)
{"core2", PROCESSOR_CORE2, CPU_CORE2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16},
{"corei7", PROCESSOR_GENERIC64, CPU_GENERIC64,
{"corei7", PROCESSOR_COREI7_64, CPU_GENERIC64,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16},
{"atom", PROCESSOR_ATOM, CPU_ATOM,
@ -3554,6 +3560,11 @@ ix86_option_override_internal (bool main_args_p)
ix86_schedule = CPU_PENTIUMPRO;
break;
case PROCESSOR_COREI7_64:
ix86_tune = PROCESSOR_COREI7_32;
ix86_schedule = CPU_PENTIUMPRO;
break;
default:
break;
}

8
gcc/config/i386/i386.h
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@ -239,6 +239,9 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32)
#define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64)
#define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64)
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
@ -2040,8 +2043,7 @@ do { \
"call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
TEXT_SECTION_ASM_OP);
/* Which processor to schedule for. The cpu attribute defines a list that
mirrors this list, so changes to i386.md must be made at the same time. */
/* Which processor to tune code generation for. */
enum processor_type
{
@ -2056,6 +2058,8 @@ enum processor_type
PROCESSOR_K8,
PROCESSOR_NOCONA,
PROCESSOR_CORE2,
PROCESSOR_COREI7_32,
PROCESSOR_COREI7_64,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_AMDFAM10,

3
gcc/doc/invoke.texi
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@ -12051,6 +12051,9 @@ SSE2 and SSE3 instruction set support.
@item core2
Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
@item corei7
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1
and SSE4.2 instruction set support.
@item atom
Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.