alpha.c (alpha_split_tfmode_pair): Rename into alpha_split_tmode_pair.
* config/alpha/alpha.c (alpha_split_tfmode_pair): Rename into alpha_split_tmode_pair. Add 'mode' and 'fixup_overlap' arguments. Test against the appropriate null constant for the mode. If 'fixup_overlap' is true, swap the operands if they overlap. (alpha_split_tfmode_frobsign): Adjust call to alpha_split_tfmode_pair. * config/alpha/alpha-protos.h (alpha_split_tfmode_pair): Rename into alpha_split_tmode_pair and adjust for above change. * config/alpha/alpha.md (movtf_internal): Adjust call to alpha_split_tfmode_pair and rely on it to swap the operands. (movti_internal): New insn and post-reload splitter. (movti): New expander. From-SVN: r109882
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
17dcd421bb
commit
b2f39494f9
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@ -1,3 +1,17 @@
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2006-01-18 Eric Botcazou <ebotcazou@adacore.com>
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* config/alpha/alpha.c (alpha_split_tfmode_pair): Rename into
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alpha_split_tmode_pair. Add 'mode' and 'fixup_overlap' arguments.
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Test against the appropriate null constant for the mode.
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If 'fixup_overlap' is true, swap the operands if they overlap.
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(alpha_split_tfmode_frobsign): Adjust call to alpha_split_tfmode_pair.
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* config/alpha/alpha-protos.h (alpha_split_tfmode_pair): Rename into
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alpha_split_tmode_pair and adjust for above change.
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* config/alpha/alpha.md (movtf_internal): Adjust call to
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alpha_split_tfmode_pair and rely on it to swap the operands.
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(movti_internal): New insn and post-reload splitter.
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(movti): New expander.
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2006-01-18 Philippe De Muyter <phdm@macqel.be>
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* config/m68k/m68k.md (*addsi3_5200): Allow addq/subq to memory
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@ -64,7 +64,7 @@ extern bool alpha_expand_mov_nobwx (enum machine_mode, rtx *);
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extern void alpha_expand_movmisalign (enum machine_mode, rtx *);
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extern void alpha_emit_floatuns (rtx[]);
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extern rtx alpha_emit_conditional_move (rtx, enum machine_mode);
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extern void alpha_split_tfmode_pair (rtx[]);
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extern void alpha_split_tmode_pair (rtx[], enum machine_mode, bool);
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extern void alpha_split_tfmode_frobsign (rtx[], rtx (*)(rtx, rtx, rtx));
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extern void alpha_expand_unaligned_load (rtx, rtx, HOST_WIDE_INT,
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HOST_WIDE_INT, int);
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@ -3198,12 +3198,17 @@ alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
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operands[1]));
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}
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/* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
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OP[0] into OP[0,1]. Naturally, output operand ordering is
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little-endian. */
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/* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
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DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
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guarantee that the sequence
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set (OP[0] OP[2])
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set (OP[1] OP[3])
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is valid. Naturally, output operand ordering is little-endian.
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This is used by *movtf_internal and *movti_internal. */
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void
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alpha_split_tfmode_pair (rtx operands[4])
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alpha_split_tmode_pair (rtx operands[4], enum machine_mode mode,
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bool fixup_overlap)
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{
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switch (GET_CODE (operands[1]))
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{
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@ -3217,8 +3222,9 @@ alpha_split_tfmode_pair (rtx operands[4])
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operands[2] = adjust_address (operands[1], DImode, 0);
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break;
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case CONST_INT:
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case CONST_DOUBLE:
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gcc_assert (operands[1] == CONST0_RTX (TFmode));
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gcc_assert (operands[1] == CONST0_RTX (mode));
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operands[2] = operands[3] = const0_rtx;
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break;
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@ -3241,6 +3247,13 @@ alpha_split_tfmode_pair (rtx operands[4])
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default:
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gcc_unreachable ();
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}
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if (fixup_overlap && reg_overlap_mentioned_p (operands[0], operands[3]))
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{
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rtx tmp;
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tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
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tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
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}
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}
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/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
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@ -3254,7 +3267,7 @@ alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
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rtx scratch;
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int move;
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alpha_split_tfmode_pair (operands);
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alpha_split_tmode_pair (operands, TFmode, false);
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/* Detect three flavors of operand overlap. */
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move = 1;
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@ -5176,13 +5176,7 @@
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 1) (match_dup 3))]
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{
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alpha_split_tfmode_pair (operands);
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if (reg_overlap_mentioned_p (operands[0], operands[3]))
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{
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rtx tmp;
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tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
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tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
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}
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alpha_split_tmode_pair (operands, TFmode, true);
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})
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(define_expand "movsf"
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@ -5668,6 +5662,80 @@
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FAIL;
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})
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;; We need to prevent reload from splitting TImode moves, because it
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;; might decide to overwrite a pointer with the value it points to.
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;; In that case we have to do the loads in the appropriate order so
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;; that the pointer is not destroyed too early.
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(define_insn_and_split "*movti_internal"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
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(match_operand:TI 1 "input_operand" "roJ,rJ"))]
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"(register_operand (operands[0], TImode)
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/* Prevent rematerialization of constants. */
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&& ! CONSTANT_P (operands[1]))
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|| reg_or_0_operand (operands[1], TImode)"
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"#"
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"reload_completed"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 1) (match_dup 3))]
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{
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alpha_split_tmode_pair (operands, TImode, true);
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})
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(define_expand "movti"
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[(set (match_operand:TI 0 "nonimmediate_operand" "")
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(match_operand:TI 1 "general_operand" ""))]
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""
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{
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if (GET_CODE (operands[0]) == MEM
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&& ! reg_or_0_operand (operands[1], TImode))
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operands[1] = force_reg (TImode, operands[1]);
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if (operands[1] == const0_rtx)
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;
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/* We must put 64-bit constants in memory. We could keep the
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32-bit constants in TImode and rely on the splitter, but
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this doesn't seem to be worth the pain. */
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else if (GET_CODE (operands[1]) == CONST_INT
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|| GET_CODE (operands[1]) == CONST_DOUBLE)
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{
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rtx in[2], out[2], target;
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gcc_assert (!no_new_pseudos);
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split_double (operands[1], &in[0], &in[1]);
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if (in[0] == const0_rtx)
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out[0] = const0_rtx;
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else
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{
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out[0] = gen_reg_rtx (DImode);
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emit_insn (gen_movdi (out[0], in[0]));
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}
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if (in[1] == const0_rtx)
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out[1] = const0_rtx;
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else
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{
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out[1] = gen_reg_rtx (DImode);
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emit_insn (gen_movdi (out[1], in[1]));
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}
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if (GET_CODE (operands[0]) != REG)
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target = gen_reg_rtx (TImode);
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else
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target = operands[0];
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emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 0), out[0]));
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emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 8), out[1]));
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if (target != operands[0])
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
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DONE;
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}
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})
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;; These are the partial-word cases.
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;;
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;; First we have the code to load an aligned word. Operand 0 is the register
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