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[PATCH][RS6000] Migrate reduction optabs in paired.md

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* gcc.target/rs6000/paired.md (reduc_smax_v2sf): Rename to...
	(reduc_smax_scal_v2sf): ...here, make result SFmode, extract element.
	(reduc_smin_v2sf): Rename to...
	(reduc_smin_scal_v2sf): ...here, make result SFmode, extract element.
	(reduc_splus_v2sf): Rename to...
	(reduc_plus_scal_v2sf): ...here, make result SFmode, extract element.

From-SVN: r232158
This commit is contained in:
Alan Lawrence 2016-01-08 11:15:58 +00:00 committed by Alan Lawrence
parent 33f0852f54
commit b356666905
2 changed files with 37 additions and 11 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2016-01-08 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/rs6000/paired.md (reduc_smax_v2sf): Rename to...
(reduc_smax_scal_v2sf): ...here, make result SFmode, extract element.
(reduc_smin_v2sf): Rename to...
(reduc_smin_scal_v2sf): ...here, make result SFmode, extract element.
(reduc_splus_v2sf): Rename to...
(reduc_plus_scal_v2sf): ...here, make result SFmode, extract element.
2016-01-08 Jakub Jelinek <jakub@redhat.com> 2016-01-08 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/69162 PR tree-optimization/69162

39
gcc/config/rs6000/paired.md
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@ -421,45 +421,62 @@
DONE; DONE;
}) })
(define_expand "reduc_smax_v2sf" (define_expand "reduc_smax_scal_v2sf"
[(match_operand:V2SF 0 "gpc_reg_operand" "=f") [(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")] (match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT" "TARGET_PAIRED_FLOAT"
{ {
rtx tmp_swap = gen_reg_rtx (V2SFmode); rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode); rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1])); emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap)); emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (operands[0], tmp, operands[1], tmp_swap, CONST0_RTX (SFmode))); emit_insn (gen_selv2sf4 (vec_res, tmp, operands[1], tmp_swap,
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE; DONE;
}) })
(define_expand "reduc_smin_v2sf" (define_expand "reduc_smin_scal_v2sf"
[(match_operand:V2SF 0 "gpc_reg_operand" "=f") [(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")] (match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT" "TARGET_PAIRED_FLOAT"
{ {
rtx tmp_swap = gen_reg_rtx (V2SFmode); rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode); rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1])); emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap)); emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (operands[0], tmp, tmp_swap, operands[1], CONST0_RTX (SFmode))); emit_insn (gen_selv2sf4 (vec_res, tmp, tmp_swap, operands[1],
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE; DONE;
}) })
(define_expand "reduc_splus_v2sf" (define_expand "reduc_plus_scal_v2sf"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f"))] (match_operand:V2SF 1 "gpc_reg_operand" "f"))]
"TARGET_PAIRED_FLOAT" "TARGET_PAIRED_FLOAT"
"
{ {
emit_insn (gen_paired_sum1 (operands[0], operands[1], operands[1], operands[1])); rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_sum1 (vec_res, operands[1], operands[1], operands[1]));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE; DONE;
}") })
(define_expand "movmisalignv2sf" (define_expand "movmisalignv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "") [(set (match_operand:V2SF 0 "nonimmediate_operand" "")