constraints.md: New.
* config/m68k/constraints.md: New. * config/m68k/m68k.h (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Remove. * config/m68k/m68k.md: Include constraints.md. * expr.c (expand_expr_real_1): Copy DECL_RTL before using it. From-SVN: r124335
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
e1f28918ef
commit
b38bab9485
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@ -1,3 +1,12 @@
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2007-05-01 Kazu Hirata <kazu@codesourcery.com>
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* config/m68k/constraints.md: New.
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* config/m68k/m68k.h (REG_CLASS_FROM_LETTER,
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CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P,
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EXTRA_CONSTRAINT): Remove.
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* config/m68k/m68k.md: Include constraints.md.
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* expr.c (expand_expr_real_1): Copy DECL_RTL before using it.
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2007-05-01 Ian Lance Taylor <iant@google.com>
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PR tree-optimization/31739
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@ -0,0 +1,107 @@
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;; Constraint definitions for m68k
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA.
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(define_register_constraint "a" "ADDR_REGS"
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"Address register.")
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(define_register_constraint "d" "DATA_REGS"
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"Data register.")
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(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
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"Floating point register.")
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(define_constraint "I"
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"Integer constant in the range 1 @dots 8, for immediate shift counts and addq."
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(and (match_code "const_int")
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(match_test "ival > 0 && ival <= 8")))
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(define_constraint "J"
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"Signed 16-bit integer constant."
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(and (match_code "const_int")
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(match_test "ival >= -0x8000 && ival <= 0x7fff")))
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(define_constraint "K"
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"Integer constant that moveq can't handle."
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(and (match_code "const_int")
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(match_test "ival < -0x80 || ival >= 0x80")))
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(define_constraint "L"
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"Integer constant in the range -8 @dots -1, for subq."
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(and (match_code "const_int")
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(match_test "ival < 0 && ival >= -8")))
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(define_constraint "M"
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"Integer constant that moveq+notb can't handle."
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(and (match_code "const_int")
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(match_test "ival < -0x100 || ival >= 0x100")))
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(define_constraint "N"
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"Integer constant in the range 24 @dots 31, for rotatert:SI 8 to 1 expressed as rotate."
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(and (match_code "const_int")
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(match_test "ival >= 24 && ival <= 31")))
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(define_constraint "O"
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"Integer constant 16, for rotate using swap."
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(and (match_code "const_int")
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(match_test "ival == 16")))
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(define_constraint "P"
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"Integer constant in the range 8 @dots 15, for rotatert:HI 8 to 1 expressed as rotate."
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(and (match_code "const_int")
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(match_test "ival >= 8 && ival <= 15")))
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(define_constraint "R"
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"Integer constant that mov3q can handle."
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(and (match_code "const_int")
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(match_test "valid_mov3q_const (ival)")))
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(define_constraint "G"
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"Defines all of the floating constants that are *NOT* 68881
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constants. This is so 68881 constants get reloaded and the fpmovecr
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is used."
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(and (match_code "const_double")
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(match_test "!(TARGET_68881 && standard_68881_constant_p (op))")))
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(define_constraint "S"
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"Used for operands that satisfy 'm' when -mpcrel is in effect."
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(and (match_code "mem")
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(match_test "TARGET_PCREL
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&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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|| GET_CODE (XEXP (op, 0)) == LABEL_REF
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|| GET_CODE (XEXP (op, 0)) == CONST)")))
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(define_constraint "T"
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"Used for operands that satisfy 's' when -mpcrel is not in effect."
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(and (match_code "symbol_ref,label_ref,const")
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(match_test "!flag_pic")))
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(define_memory_constraint "Q"
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"Means address register indirect addressing mode."
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(and (match_code "mem")
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(match_test "m68k_matches_q_p (op)")))
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(define_constraint "U"
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"Used for register offset addressing."
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(and (match_code "mem")
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(match_test "m68k_matches_u_p (op)")))
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(define_constraint "W"
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"Used for const_call_operands."
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(match_operand 0 "const_call_operand"))
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@ -485,74 +485,6 @@ extern enum reg_class regno_reg_class[];
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#define INDEX_REG_CLASS GENERAL_REGS
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#define BASE_REG_CLASS ADDR_REGS
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/* We do a trick here to modify the effective constraints on the
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machine description; we zorch the constraint letters that aren't
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appropriate for a specific target. This allows us to guarantee
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that a specific kind of register will not be used for a given target
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without fiddling with the register classes above. */
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#define REG_CLASS_FROM_LETTER(C) \
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((C) == 'a' ? ADDR_REGS : \
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((C) == 'd' ? DATA_REGS : \
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((C) == 'f' ? (TARGET_HARD_FLOAT ? \
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FP_REGS : NO_REGS) : \
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NO_REGS)))
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/* For the m68k, `I' is used for the range 1 to 8
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allowed as immediate shift counts and in addq.
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`J' is used for the range of signed numbers that fit in 16 bits.
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`K' is for numbers that moveq can't handle.
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`L' is for range -8 to -1, range of values that can be added with subq.
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`M' is for numbers that moveq+notb can't handle.
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'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
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'O' is for 16 (for rotate using swap).
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'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate.
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'R' is for numbers that mov3q can handle. */
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
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(C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
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(C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
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(C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
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(C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
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(C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
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(C) == 'O' ? (VALUE) == 16 : \
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(C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : \
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(C) == 'R' ? valid_mov3q_const (VALUE) : 0)
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/* "G" defines all of the floating constants that are *NOT* 68881
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constants. This is so 68881 constants get reloaded and the
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fpmovecr is used. */
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#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
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/* `Q' means address register indirect addressing mode.
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`S' is for operands that satisfy 'm' when -mpcrel is in effect.
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`T' is for operands that satisfy 's' when -mpcrel is not in effect.
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`U' is for register offset addressing.
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`W' is for const_call_operands. */
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#define EXTRA_CONSTRAINT(OP,CODE) \
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((CODE) == 'S' \
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? (TARGET_PCREL \
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&& GET_CODE (OP) == MEM \
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&& (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
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|| GET_CODE (XEXP (OP, 0)) == LABEL_REF \
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|| GET_CODE (XEXP (OP, 0)) == CONST)) \
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: \
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(CODE) == 'T' \
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? (!flag_pic \
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&& (GET_CODE (OP) == SYMBOL_REF \
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|| GET_CODE (OP) == LABEL_REF \
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|| GET_CODE (OP) == CONST)) \
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: \
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(CODE) == 'Q' \
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? m68k_matches_q_p (OP) \
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: \
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(CODE) == 'U' \
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? m68k_matches_u_p (OP) \
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: \
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(CODE) == 'W' \
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? const_call_operand (OP, VOIDmode) \
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: 0)
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#define PREFERRED_RELOAD_CLASS(X,CLASS) \
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m68k_preferred_reload_class (X, CLASS)
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@ -135,6 +135,7 @@
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])
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(include "predicates.md")
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(include "constraints.md")
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;; Mode macros for floating point operations.
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;; Valid floating point modes
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@ -6968,6 +6968,7 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
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case RESULT_DECL:
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decl_rtl = DECL_RTL (exp);
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gcc_assert (decl_rtl);
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decl_rtl = copy_rtx (decl_rtl);
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/* Ensure variable marked as used even if it doesn't go through
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a parser. If it hasn't be used yet, write out an external
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