Fix compile time warnings about signed vs unsigned constants
From-SVN: r31298
This commit is contained in:
Nick Clifton
Nick Clifton
parent
3a5a428223
commit
b39e12403c
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@ -1,3 +1,10 @@
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2000-01-09 Nick Clifton <nickc@cygnus.com>
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* config/arm/arm.c: Fix compile time warnings about signed vs
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unsigned constants.
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* config/arm/arm.h: Fix compile time warnings about signed vs
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unsigned constants.
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2000-01-09 Philip Blundell <philb@gnu.org>
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* config/arm/arm.c (output_return_instruction): Use `ldr' rather
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@ -658,10 +658,10 @@ const_ok_for_arm (i)
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/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
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be all zero, or all one. */
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if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
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&& ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
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if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
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&& ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
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!= ((~(unsigned HOST_WIDE_INT) 0)
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& ~(unsigned HOST_WIDE_INT) 0xffffffff)))
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& ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
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return FALSE;
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/* Fast return for 0 and powers of 2 */
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@ -670,11 +670,11 @@ const_ok_for_arm (i)
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do
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{
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if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
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if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
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return TRUE;
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mask =
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(mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
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>> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
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(mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
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>> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
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} while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
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return FALSE;
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@ -795,7 +795,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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int set_zero_bit_copies = 0;
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int insns = 0;
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unsigned HOST_WIDE_INT temp1, temp2;
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unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
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unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
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/* find out which operations are safe for a given CODE. Also do a quick
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check for degenerate cases; these can occur when DImode operations
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@ -814,7 +814,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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break;
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case IOR:
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if (remainder == 0xffffffff)
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if (remainder == 0xffffffffUL)
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{
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if (generate)
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emit_insn (gen_rtx_SET (VOIDmode, target,
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@ -838,7 +838,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
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return 1;
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}
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if (remainder == 0xffffffff)
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if (remainder == 0xffffffffUL)
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{
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if (reload_completed && rtx_equal_p (target, source))
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return 0;
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@ -858,7 +858,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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emit_insn (gen_rtx_SET (VOIDmode, target, source));
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return 1;
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}
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if (remainder == 0xffffffff)
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if (remainder == 0xffffffffUL)
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{
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if (generate)
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emit_insn (gen_rtx_SET (VOIDmode, target,
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@ -988,15 +988,15 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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word. We only look for the simplest cases, to do more would cost
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too much. Be careful, however, not to generate this when the
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alternative would take fewer insns. */
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if (val & 0xffff0000)
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if (val & 0xffff0000UL)
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{
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temp1 = remainder & 0xffff0000;
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temp1 = remainder & 0xffff0000UL;
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temp2 = remainder & 0x0000ffff;
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/* Overlaps outside this range are best done using other methods. */
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for (i = 9; i < 24; i++)
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{
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if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
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if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
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&& ! const_ok_for_arm (temp2))
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{
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rtx new_src = (subtargets
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@ -1134,11 +1134,11 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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/* See if two shifts will do 2 or more insn's worth of work. */
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if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
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{
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HOST_WIDE_INT shift_mask = ((0xffffffff
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HOST_WIDE_INT shift_mask = ((0xffffffffUL
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<< (32 - clear_sign_bit_copies))
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& 0xffffffff);
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& 0xffffffffUL);
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if ((remainder | shift_mask) != 0xffffffff)
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if ((remainder | shift_mask) != 0xffffffffUL)
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{
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if (generate)
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{
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@ -1171,7 +1171,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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{
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HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
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if ((remainder | shift_mask) != 0xffffffff)
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if ((remainder | shift_mask) != 0xffffffffUL)
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{
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if (generate)
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{
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@ -1213,9 +1213,9 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
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num_bits_set++;
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if (code == AND || (can_invert && num_bits_set > 16))
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remainder = (~remainder) & 0xffffffff;
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remainder = (~remainder) & 0xffffffffUL;
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else if (code == PLUS && num_bits_set > 16)
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remainder = (-remainder) & 0xffffffff;
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remainder = (-remainder) & 0xffffffffUL;
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else
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{
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can_invert = 0;
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@ -1809,7 +1809,7 @@ arm_rtx_costs (x, code)
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if (GET_CODE (XEXP (x, 1)) == CONST_INT)
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{
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unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
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& (unsigned HOST_WIDE_INT) 0xffffffff);
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& (unsigned HOST_WIDE_INT) 0xffffffffUL);
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int add_cost = const_ok_for_arm (i) ? 4 : 8;
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int j;
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/* Tune as appropriate */
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@ -3764,9 +3764,9 @@ arm_reload_in_hi (operands)
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if (lo == 4095)
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lo &= 0x7ff;
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hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
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^ (HOST_WIDE_INT) 0x80000000)
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- (HOST_WIDE_INT) 0x80000000);
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hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
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^ (HOST_WIDE_INT) 0x80000000UL)
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- (HOST_WIDE_INT) 0x80000000UL);
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if (hi + lo != offset)
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abort ();
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@ -3910,9 +3910,9 @@ arm_reload_out_hi (operands)
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if (lo == 4095)
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lo &= 0x7ff;
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hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
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^ (HOST_WIDE_INT) 0x80000000)
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- (HOST_WIDE_INT) 0x80000000);
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hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
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^ (HOST_WIDE_INT) 0x80000000UL)
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- (HOST_WIDE_INT) 0x80000000UL);
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if (hi + lo != offset)
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abort ();
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@ -2041,10 +2041,10 @@ extern struct rtx_def * arm_compare_op1;
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#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
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(HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
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: (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
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(((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
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: (((x) & (unsigned HOST_WIDE_INT) 0xffffffffUL) | \
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(((x) & (unsigned HOST_WIDE_INT) 0x80000000UL) \
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? ((~ (HOST_WIDE_INT) 0) \
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& ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
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& ~ (unsigned HOST_WIDE_INT) 0xffffffffUL) \
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: 0))))
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/* Output the address of an operand. */
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