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vect-mull-compile.c: Explicitly scan for instructions generated instead of number of occurances. 

2013-01-08  Tejas Belagod  <tejas.belagod@arm.com>

	* gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for 
	instructions generated instead of number of occurances.

From-SVN: r195024
This commit is contained in:
Tejas Belagod 2013-01-08 16:23:38 +00:00 committed by Tejas Belagod
parent a02ad1aa17
commit b4208463a3
2 changed files with 17 additions and 4 deletions
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5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for
instructions generated instead of number of occurances.
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New.

16
gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
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@ -10,7 +10,15 @@ DEF_MULL2 (DEF_MULLB)
DEF_MULL2 (DEF_MULLH)
DEF_MULL2 (DEF_MULLS)
/* { dg-final { scan-assembler-times "smull v" 3 } } */
/* { dg-final { scan-assembler-times "smull2 v" 3 } } */
/* { dg-final { scan-assembler-times "umull v" 3 } } */
/* { dg-final { scan-assembler-times "umull2 v" 3 } } */
/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */
/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */
/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */
/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */
/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */
/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */
/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */
/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */