From b4e239708370a115fe062454b8fa36b96ee38111 Mon Sep 17 00:00:00 2001 From: Joern Rennecke Date: Mon, 11 Nov 2013 10:22:58 +0000 Subject: [PATCH] * config/arc/arc.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define. From-SVN: r204666 --- gcc/ChangeLog | 4 ++++ gcc/config/arc/arc.h | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ea7d382357a..6c55b69e660 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2013-11-11 Joern Rennecke + + * config/arc/arc.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define. + 2013-11-08 Jeff Law * tree-ssa-threadupdate.c (mark_threaded_blocks): Truncate jump diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 87908d41afc..cc49c553c55 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -1087,6 +1087,22 @@ arc_select_cc_mode (OP, X, Y) expensive than reg->reg moves. */ #define BRANCH_COST(speed_p, predictable_p) 2 +/* Scc sets the destination to 1 and then conditionally zeroes it. + Best case, ORed SCCs can be made into clear - condset - condset. + But it could also end up as five insns. So say it costs four on + average. + These extra instructions - and the second comparison - will also be + an extra cost if the first comparison would have been decisive. + So get an average saving, with a probability of the first branch + beging decisive of p0, we want: + p0 * (branch_cost - 4) > (1 - p0) * 5 + ??? We don't get to see that probability to evaluate, so we can + only wildly guess that it might be 50%. + ??? The compiler also lacks the notion of branch predictability. */ +#define LOGICAL_OP_NON_SHORT_CIRCUIT \ + (BRANCH_COST (optimize_function_for_speed_p (cfun), \ + false) > 9) + /* Nonzero if access to memory by bytes is slow and undesirable. For RISC chips, it means that access to memory by bytes is no better than access by words when possible, so grab a whole word