rs6000.md (iorxor): New code_iterator.
2014-09-21 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.md (iorxor): New code_iterator. (iorxor): New code_attr. (IORXOR): New code_attr. (*and<mode>3, *and<mode>3_dot, *and<mode>3_dot2): Delete. (ior<mode>3, xor<mode>3): Delete. (<iorxor><mode>3): New. (splitter for "big" integer ior, xor): New. (*bool<mode>3): Move. Also handle AND. (*bool<mode>3_dot, *bool<mode>3_dot2): Also handle AND. (splitter for "big" integer ior, xor): Delete. From-SVN: r215433
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Segher Boessenkool
Segher Boessenkool
parent
9f0a331352
commit
b4e2da9e22
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@ -1,3 +1,16 @@
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (iorxor): New code_iterator.
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(iorxor): New code_attr.
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(IORXOR): New code_attr.
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(*and<mode>3, *and<mode>3_dot, *and<mode>3_dot2): Delete.
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(ior<mode>3, xor<mode>3): Delete.
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(<iorxor><mode>3): New.
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(splitter for "big" integer ior, xor): New.
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(*bool<mode>3): Move. Also handle AND.
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(*bool<mode>3_dot, *bool<mode>3_dot2): Also handle AND.
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(splitter for "big" integer ior, xor): Delete.
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (*neg<mode>2_internal): Delete.
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@ -438,6 +438,11 @@
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(simple_return "1")])
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(define_code_attr return_str [(return "") (simple_return "simple_")])
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; Logical operators.
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(define_code_iterator iorxor [ior xor])
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(define_code_attr iorxor [(ior "ior") (xor "xor")])
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(define_code_attr IORXOR [(ior "IOR") (xor "XOR")])
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; Signed/unsigned variants of ops.
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(define_code_iterator any_extend [sign_extend zero_extend])
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(define_code_attr u [(sign_extend "") (zero_extend "u")])
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@ -2640,61 +2645,6 @@
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})
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(define_insn "*and<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "gpc_reg_operand" "r")))]
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""
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"and %0,%1,%2"
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[(set_attr "type" "logical")])
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(define_insn_and_split "*and<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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and. %0,%1,%2
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(and:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "logical")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn_and_split "*and<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(and:GPR (match_dup 1)
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(match_dup 2)))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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and. %0,%1,%2
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(and:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "logical")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn "and<mode>3_imm"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
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@ -2913,15 +2863,15 @@
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[(set_attr "length" "8")])
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(define_expand "ior<mode>3"
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(define_expand "<iorxor><mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_cint_operand" "")))]
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(iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_cint_operand" "")))]
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""
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{
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if (<MODE>mode == DImode && !TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, IOR, false, false, false);
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rs6000_split_logical (operands, <IORXOR>, false, false, false);
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DONE;
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}
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@ -2930,12 +2880,13 @@
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (<MODE>mode));
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HOST_WIDE_INT value = INTVAL (operands[2]);
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HOST_WIDE_INT lo = value & 0xffff;
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HOST_WIDE_INT hi = value - lo;
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emit_insn (gen_ior<mode>3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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emit_insn (gen_<iorxor><mode>3 (tmp, operands[1], GEN_INT (hi)));
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emit_insn (gen_<iorxor><mode>3 (operands[0], tmp, GEN_INT (lo)));
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DONE;
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}
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@ -2943,45 +2894,30 @@
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operands[2] = force_reg (<MODE>mode, operands[2]);
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})
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(define_expand "xor<mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_cint_operand" "")))]
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(define_split
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "non_logical_cint_operand" "")))]
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""
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[(set (match_dup 3)
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(iorxor:GPR (match_dup 1)
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(match_dup 4)))
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(set (match_dup 0)
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(iorxor:GPR (match_dup 3)
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(match_dup 5)))]
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{
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if (<MODE>mode == DImode && !TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, XOR, false, false, false);
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DONE;
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}
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if (non_logical_cint_operand (operands[2], <MODE>mode))
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{
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rtx tmp = ((!can_create_pseudo_p ()
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operands[3] = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (<MODE>mode));
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HOST_WIDE_INT value = INTVAL (operands[2]);
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emit_insn (gen_xor<mode>3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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HOST_WIDE_INT value = INTVAL (operands[2]);
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HOST_WIDE_INT lo = value & 0xffff;
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HOST_WIDE_INT hi = value - lo;
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emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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DONE;
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}
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if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
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operands[2] = force_reg (<MODE>mode, operands[2]);
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operands[4] = GEN_INT (hi);
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operands[5] = GEN_INT (lo);
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})
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(define_insn "*bool<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "gpc_reg_operand" "r")]))]
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""
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"%q3 %0,%1,%2"
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[(set_attr "type" "logical")])
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(define_insn "*bool<mode>3_imm"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(match_operator:GPR 3 "boolean_or_operator"
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@ -2991,9 +2927,18 @@
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"%q3i%e2 %0,%1,%u2"
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[(set_attr "type" "logical")])
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(define_insn "*bool<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(match_operator:GPR 3 "boolean_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "gpc_reg_operand" "r")]))]
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""
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"%q3 %0,%1,%2"
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[(set_attr "type" "logical")])
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(define_insn_and_split "*bool<mode>3_dot"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:GPR 3 "boolean_or_operator"
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(compare:CC (match_operator:GPR 3 "boolean_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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@ -3015,7 +2960,7 @@
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(define_insn_and_split "*bool<mode>3_dot2"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:GPR 3 "boolean_or_operator"
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(compare:CC (match_operator:GPR 3 "boolean_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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@ -3036,27 +2981,6 @@
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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;; Split a logical operation that we can't do in one insn into two insns,
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;; each of which does one 16-bit part. This is used by combine.
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(define_split
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "non_logical_cint_operand" "")]))]
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""
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 0) (match_dup 5))]
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{
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rtx i;
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i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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operands[1], i);
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i = GEN_INT (INTVAL (operands[2]) & 0xffff);
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operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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operands[0], i);
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})
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(define_insn "*boolc<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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