re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)
PR target/51244 * config/sh/sh.md (negsi_cond, negdi_cond, stack_protect_test): Remove get_t_reg_rtx when invoking gen_branch_true or gen_branch_false. (*zero_extend<mode>si2_compact): Convert to insn_and_split. Convert zero extensions of T bit stores to reg moves in splitter. Remove obsolete unnamed peephole2 that caught zero extensions after negc T bit stores. (*branch_true_eq, *branch_false_ne): Delete. (branch_true, branch_false): Convert insn to expander. Move actual insn logic to... (*cbranch_t): ...this new insn_and_split. Try to find preceding redundant T bit stores and tests and combine them with the conditional branch if possible in the splitter. (movrt_xor, *movt_movrt): New insn_and_split. * config/sh/predicates.md (cbranch_treg_value): New predicate. * config/sh/sh-protos.h (sh_eval_treg_value): Forward declare... * config/sh/sh.c (sh_eval_treg_value): ...this new function. (expand_cbranchsi4, expand_cbranchdi4): Remove get_t_reg_rtx when invoking gen_branch_true or gen_branch_false. PR target/51244 * gcc.target/sh/pr51244-13.c: New. * gcc.target/sh/pr51244-14.c: New. * gcc.target/sh/pr51244-15.c: New. * gcc.target/sh/pr51244-16.c: New. From-SVN: r192387
This commit is contained in:
Oleg Endo
parent
76a2a3f738
commit
b4eca9c8df
@ -1,3 +1,25 @@
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2012-10-12 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/51244
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* config/sh/sh.md (negsi_cond, negdi_cond, stack_protect_test): Remove
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get_t_reg_rtx when invoking gen_branch_true or gen_branch_false.
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(*zero_extend<mode>si2_compact): Convert to insn_and_split. Convert
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zero extensions of T bit stores to reg moves in splitter. Remove
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obsolete unnamed peephole2 that caught zero extensions after negc T bit
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stores.
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(*branch_true_eq, *branch_false_ne): Delete.
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(branch_true, branch_false): Convert insn to expander. Move actual
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insn logic to...
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(*cbranch_t): ...this new insn_and_split. Try to find preceding
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redundant T bit stores and tests and combine them with the conditional
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branch if possible in the splitter.
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(movrt_xor, *movt_movrt): New insn_and_split.
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* config/sh/predicates.md (cbranch_treg_value): New predicate.
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* config/sh/sh-protos.h (sh_eval_treg_value): Forward declare...
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* config/sh/sh.c (sh_eval_treg_value): ...this new function.
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(expand_cbranchsi4, expand_cbranchdi4): Remove get_t_reg_rtx
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when invoking gen_branch_true or gen_branch_false.
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2012-10-11 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (IMODE): New mode iterator.
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@ -1048,6 +1048,14 @@
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}
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})
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;; A predicate that returns true if OP is a valid construct around the T bit
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;; that can be used as an operand for conditional branches.
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(define_predicate "cbranch_treg_value"
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(match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
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{
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return sh_eval_treg_value (op) >= 0;
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})
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;; Returns true of OP is arith_reg_operand or t_reg_operand.
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(define_predicate "arith_reg_or_t_reg_operand"
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(ior (match_operand 0 "arith_reg_operand")
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@ -162,6 +162,7 @@ extern bool sh_cfun_trap_exit_p (void);
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extern void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
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enum machine_mode mode = VOIDmode);
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extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem);
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extern int sh_eval_treg_value (rtx op);
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#endif /* RTX_CODE */
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extern void sh_cpu_cpp_builtins (cpp_reader* pfile);
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@ -2059,7 +2059,7 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
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void
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expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
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{
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rtx (*branch_expander) (rtx, rtx) = gen_branch_true;
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rtx (*branch_expander) (rtx) = gen_branch_true;
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comparison = prepare_cbranch_operands (operands, SImode, comparison);
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switch (comparison)
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{
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@ -2071,7 +2071,7 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
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emit_insn (gen_rtx_SET (VOIDmode, get_t_reg_rtx (),
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gen_rtx_fmt_ee (comparison, SImode,
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operands[1], operands[2])));
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rtx jump = emit_jump_insn (branch_expander (operands[3], get_t_reg_rtx ()));
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rtx jump = emit_jump_insn (branch_expander (operands[3]));
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if (probability >= 0)
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add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
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}
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@ -2123,7 +2123,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
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if (TARGET_CMPEQDI_T)
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{
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emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
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emit_jump_insn (gen_branch_true (operands[3], get_t_reg_rtx ()));
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emit_jump_insn (gen_branch_true (operands[3]));
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return true;
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}
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msw_skip = NE;
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@ -2150,7 +2150,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
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if (TARGET_CMPEQDI_T)
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{
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emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
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emit_jump_insn (gen_branch_false (operands[3], get_t_reg_rtx ()));
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emit_jump_insn (gen_branch_false (operands[3]));
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return true;
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}
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msw_taken = NE;
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@ -2281,6 +2281,43 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
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return true;
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}
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/* Given an operand, return 1 if the evaluated operand plugged into an
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if_then_else will result in a branch_true, 0 if branch_false, or
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-1 if neither nor applies. The truth table goes like this:
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op | cmpval | code | result
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---------+--------+---------+--------------------
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T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
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T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
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T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
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T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
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!T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
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!T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
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!T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
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!T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
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int
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sh_eval_treg_value (rtx op)
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{
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enum rtx_code code = GET_CODE (op);
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if ((code != EQ && code != NE) || !CONST_INT_P (XEXP (op, 1)))
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return -1;
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int cmpop = code == EQ ? 1 : 0;
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int cmpval = INTVAL (XEXP (op, 1));
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if (cmpval != 0 && cmpval != 1)
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return -1;
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int t;
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if (t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
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t = 0;
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else if (negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
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t = 1;
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else
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return -1;
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return t ^ (cmpval == cmpop);
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}
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/* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
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static void
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@ -2485,9 +2522,9 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
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sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
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if (branch_code == code)
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emit_jump_insn (gen_branch_true (operands[3], get_t_reg_rtx ()));
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emit_jump_insn (gen_branch_true (operands[3]));
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else
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emit_jump_insn (gen_branch_false (operands[3], get_t_reg_rtx ()));
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emit_jump_insn (gen_branch_false (operands[3]));
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}
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void
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@ -2521,7 +2558,7 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
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{
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lab = gen_label_rtx ();
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sh_emit_scc_to_t (EQ, op0, op1);
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emit_jump_insn (gen_branch_true (lab, get_t_reg_rtx ()));
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emit_jump_insn (gen_branch_true (lab));
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code = GT;
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}
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else
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@ -5322,8 +5322,8 @@ label:
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emit_insn (gen_movsi (operands[0], operands[1]));
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emit_jump_insn (INTVAL (operands[3])
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? gen_branch_true (skip_neg_label, get_t_reg_rtx ())
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: gen_branch_false (skip_neg_label, get_t_reg_rtx ()));
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? gen_branch_true (skip_neg_label)
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: gen_branch_false (skip_neg_label));
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emit_label_after (skip_neg_label,
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emit_insn (gen_negsi2 (operands[0], operands[1])));
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@ -5391,8 +5391,8 @@ label:
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emit_insn (gen_movsi (high_dst, high_src));
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emit_jump_insn (INTVAL (operands[3])
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? gen_branch_true (skip_neg_label, get_t_reg_rtx ())
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: gen_branch_false (skip_neg_label, get_t_reg_rtx ()));
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? gen_branch_true (skip_neg_label)
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: gen_branch_false (skip_neg_label));
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if (!INTVAL (operands[3]))
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emit_insn (gen_clrt ());
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@ -5575,11 +5575,57 @@ label:
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[(set (match_operand:SI 0 "arith_reg_dest")
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(zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
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(define_insn "*zero_extend<mode>si2_compact"
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(define_insn_and_split "*zero_extend<mode>si2_compact"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
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"TARGET_SH1"
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"extu.<bw> %1,%0"
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"&& can_create_pseudo_p ()"
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[(set (match_dup 0) (match_dup 2))]
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{
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/* Sometimes combine fails to combine a T bit or negated T bit store to a
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reg with a following zero extension. In the split pass after combine,
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try to figure the extended reg was set. If it originated from the T
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bit we can replace the zero extension with a reg move, which will be
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eliminated. Notice that this also helps the *cbranch_t splitter when
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it tries to post-combine tests and conditional branches, as it does not
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check for zero extensions. */
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rtx ext_reg;
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if (REG_P (operands[1]))
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ext_reg = operands[1];
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else if (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1])))
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ext_reg = SUBREG_REG (operands[1]);
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else
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FAIL;
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/* Reg moves must be of the same mode. */
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if (GET_MODE (ext_reg) != SImode)
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FAIL;
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operands[2] = NULL_RTX;
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for (rtx i = prev_nonnote_insn_bb (curr_insn); i != NULL_RTX;
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i = prev_nonnote_insn_bb (i))
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{
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if (LABEL_P (i) || BARRIER_P (i))
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break;
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if (!NONJUMP_INSN_P (i))
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continue;
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if (reg_set_p (ext_reg, i))
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{
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rtx set_op = XEXP (set_of (ext_reg, i), 1);
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if (set_op == NULL_RTX)
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break;
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if (t_reg_operand (set_op, VOIDmode)
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|| negt_reg_operand (set_op, VOIDmode))
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operands[2] = ext_reg;
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break;
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}
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}
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if (operands[2] == NULL_RTX)
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FAIL;
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}
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[(set_attr "type" "arith")])
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(define_insn "*zero_extendhisi2_media"
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@ -8108,47 +8154,126 @@ label:
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;; Define the real conditional branch instructions.
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;; ------------------------------------------------------------------------
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(define_insn "branch_true"
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[(set (pc) (if_then_else (ne (match_operand 1 "t_reg_operand" "")
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(define_expand "branch_true"
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[(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
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(label_ref (match_operand 0))
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(pc)))]
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"TARGET_SH1"
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{
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return output_branch (1, insn, operands);
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}
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[(set_attr "type" "cbranch")])
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"TARGET_SH1")
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(define_insn "*branch_true_eq"
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[(set (pc) (if_then_else (eq (match_operand 1 "t_reg_operand" "")
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(const_int 1))
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(label_ref (match_operand 0 "" ""))
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(define_expand "branch_false"
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[(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
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(label_ref (match_operand 0))
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(pc)))]
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"TARGET_SH1"
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{
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return output_branch (1, insn, operands);
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}
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[(set_attr "type" "cbranch")])
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"TARGET_SH1")
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(define_insn "branch_false"
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[(set (pc) (if_then_else (eq (match_operand 1 "t_reg_operand" "")
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(define_insn_and_split "*cbranch_t"
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[(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
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(label_ref (match_operand 0))
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(pc)))]
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"TARGET_SH1"
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{
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return output_branch (0, insn, operands);
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return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
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}
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[(set_attr "type" "cbranch")])
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(define_insn "*branch_false_ne"
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[(set (pc) (if_then_else (ne (match_operand 1 "t_reg_operand" "")
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(const_int 1))
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(label_ref (match_operand 0 "" ""))
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"&& can_create_pseudo_p ()"
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[(set (pc) (if_then_else (eq (reg:SI T_REG) (match_dup 2))
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(label_ref (match_dup 0))
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(pc)))]
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"TARGET_SH1"
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{
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return output_branch (0, insn, operands);
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/* Try to find missed test and branch combine opportunities which result
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in redundant T bit tests before conditional branches.
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FIXME: Probably this would not be needed if CCmode was used
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together with TARGET_FIXED_CONDITION_CODE_REGS. */
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const int treg_value = sh_eval_treg_value (operands[1]);
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operands[2] = NULL_RTX;
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/* Scan the insns backwards for an insn that sets the T bit by testing a
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reg against zero like:
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(set (reg T_REG) (eq (reg) (const_int 0))) */
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rtx testing_insn = NULL_RTX;
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rtx tested_reg = NULL_RTX;
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for (rtx i = prev_nonnote_insn_bb (curr_insn); i != NULL_RTX;
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i = prev_nonnote_insn_bb (i))
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{
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if (LABEL_P (i) || BARRIER_P (i))
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break;
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if (!NONJUMP_INSN_P (i))
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continue;
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rtx p = PATTERN (i);
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if (p != NULL_RTX
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&& GET_CODE (p) == SET && t_reg_operand (XEXP (p, 0), VOIDmode)
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&& GET_CODE (XEXP (p, 1)) == EQ
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&& REG_P (XEXP (XEXP (p, 1), 0))
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&& satisfies_constraint_Z (XEXP (XEXP (p, 1), 1)))
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{
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testing_insn = i;
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tested_reg = XEXP (XEXP (p, 1), 0);
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break;
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}
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}
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if (testing_insn == NULL_RTX)
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FAIL;
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/* Continue scanning the insns backwards and try to find the insn that
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sets the tested reg which we found above. If the reg is set by storing
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the T bit or the negated T bit we can eliminate the test insn before
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the branch. Notice that the branch condition has to be inverted if the
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test is eliminated. */
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/* If the T bit is used between the testing insn and the brach insn
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leave it alone. */
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if (reg_used_between_p (get_t_reg_rtx (), testing_insn, curr_insn))
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FAIL;
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for (rtx i = prev_nonnote_insn_bb (testing_insn); i != NULL_RTX;
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i = prev_nonnote_insn_bb (i))
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{
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if (LABEL_P (i) || BARRIER_P (i))
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break;
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if (!NONJUMP_INSN_P (i))
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continue;
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if (reg_set_p (tested_reg, i))
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{
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const_rtx tested_reg_set = set_of (tested_reg, i);
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/* It could also be a clobber... */
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if (tested_reg_set == NULL_RTX || GET_CODE (tested_reg_set) != SET)
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break;
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rtx set_op1 = XEXP (tested_reg_set, 1);
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if (t_reg_operand (set_op1, VOIDmode))
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operands[2] = GEN_INT (treg_value ^ 1);
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else if (negt_reg_operand (set_op1, VOIDmode))
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operands[2] = GEN_INT (treg_value);
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else if (REG_P (set_op1))
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{
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/* If it's a reg-reg copy follow the copied reg. This can
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happen e.g. when T bit store zero-extensions are
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eliminated. */
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tested_reg = set_op1;
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continue;
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}
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/* It's only safe to remove the testing insn if the T bit is not
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modified between the testing insn and the insn that stores the
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T bit. Notice that some T bit stores such as negc also modify
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the T bit. */
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if (modified_between_p (get_t_reg_rtx (), i, testing_insn)
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|| modified_in_p (get_t_reg_rtx (), i))
|
||||
operands[2] = NULL_RTX;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (operands[2] == NULL_RTX)
|
||||
FAIL;
|
||||
|
||||
set_insn_deleted (testing_insn);
|
||||
}
|
||||
[(set_attr "type" "cbranch")])
|
||||
|
||||
@ -10960,25 +11085,53 @@ label:
|
||||
(set (reg:SI T_REG) (const_int 1))
|
||||
(use (match_dup 2))])])
|
||||
|
||||
;; In some cases the zero extension does not get combined away and a
|
||||
;; sequence like the following might remain:
|
||||
;; mov #-1,r2
|
||||
;; tst r1,r1
|
||||
;; negc r2,r1
|
||||
;; extu.b r1,r1
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "arith_reg_dest" "")
|
||||
(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
|
||||
(set (reg:SI T_REG) (const_int 1))
|
||||
(use (match_operand:SI 2 "arith_reg_operand" ""))])
|
||||
(set (match_dup 0)
|
||||
(zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
|
||||
"TARGET_SH1 && REGNO (operands[0]) == REGNO (operands[3])"
|
||||
[(parallel
|
||||
[(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
|
||||
(set (reg:SI T_REG) (const_int 1))
|
||||
(use (match_dup 2))])])
|
||||
;; Store the negated T bit in a reg using r0 and xor. This one doesn't
|
||||
;; clobber the T bit, which is useful when storing the T bit and the
|
||||
;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
|
||||
;; Usually we don't want this insn to be matched, except for cases where the
|
||||
;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
|
||||
(define_insn_and_split "movrt_xor"
|
||||
[(set (match_operand:SI 0 "arith_reg_dest" "=z")
|
||||
(xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
|
||||
(use (reg:SI T_REG))]
|
||||
"TARGET_SH1 && !TARGET_SH2A"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (reg:SI T_REG))
|
||||
(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
|
||||
|
||||
;; Store the T bit and the negated T bit in two regs in parallel. There is
|
||||
;; no real insn to do that, but specifying this pattern will give combine
|
||||
;; some opportunities.
|
||||
(define_insn_and_split "*movt_movrt"
|
||||
[(parallel [(set (match_operand:SI 0 "arith_reg_dest")
|
||||
(match_operand:SI 1 "negt_reg_operand"))
|
||||
(set (match_operand:SI 2 "arith_reg_dest")
|
||||
(match_operand:SI 3 "t_reg_operand"))])]
|
||||
"TARGET_SH1"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
rtx i = TARGET_SH2A
|
||||
? gen_movrt (operands[0], get_t_reg_rtx ())
|
||||
: gen_movrt_xor (operands[0], get_t_reg_rtx ());
|
||||
|
||||
emit_insn (i);
|
||||
emit_insn (gen_movt (operands[2], get_t_reg_rtx ()));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn_and_split "*movt_movrt"
|
||||
[(parallel [(set (match_operand:SI 0 "arith_reg_dest")
|
||||
(match_operand:SI 1 "t_reg_operand"))
|
||||
(set (match_operand:SI 2 "arith_reg_dest")
|
||||
(match_operand:SI 3 "negt_reg_operand"))])]
|
||||
"TARGET_SH1"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(parallel [(set (match_dup 2) (match_dup 3))
|
||||
(set (match_dup 0) (match_dup 1))])])
|
||||
|
||||
;; Use negc to store the T bit in a MSB of a reg in the following way:
|
||||
;; T = 1: 0x80000000 -> reg
|
||||
@ -15165,7 +15318,7 @@ label:
|
||||
else
|
||||
{
|
||||
emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
|
||||
emit_jump_insn (gen_branch_true (operands[2], get_t_reg_rtx ()));
|
||||
emit_jump_insn (gen_branch_true (operands[2]));
|
||||
}
|
||||
|
||||
DONE;
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2012-10-12 Oleg Endo <olegendo@gcc.gnu.org>
|
||||
|
||||
PR target/51244
|
||||
* gcc.target/sh/pr51244-13.c: New.
|
||||
* gcc.target/sh/pr51244-14.c: New.
|
||||
* gcc.target/sh/pr51244-15.c: New.
|
||||
* gcc.target/sh/pr51244-16.c: New.
|
||||
|
||||
2012-10-11 Paolo Carlini <paolo.carlini@oracle.com>
|
||||
|
||||
PR c++/51878
|
||||
|
||||
85
gcc/testsuite/gcc.target/sh/pr51244-13.c
Normal file
85
gcc/testsuite/gcc.target/sh/pr51244-13.c
Normal file
@ -0,0 +1,85 @@
|
||||
/* This is a case extracted from CSiBE which contained the following
|
||||
sequence:
|
||||
shll r0
|
||||
movt r0
|
||||
tst r0,r0
|
||||
bf .L11
|
||||
where the 'tst r0,r0' before the branch can be omitted by inverting the
|
||||
branch condition. The tested function contains two other tst insns. If
|
||||
everything goes as expected we will be seeing only those other two tst
|
||||
insns. */
|
||||
/* { dg-do compile { target "sh*-*-*" } } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
|
||||
/* { dg-final { scan-assembler-times "tst" 2 } } */
|
||||
|
||||
static __inline__ int
|
||||
__test_bit (unsigned long nr, volatile void * addr)
|
||||
{
|
||||
/* This is on purpose. */
|
||||
int oldbit;
|
||||
return oldbit & 1;
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
__constant_test_bit (unsigned long nr, volatile void * addr)
|
||||
{
|
||||
return (((volatile char *) addr)[(nr>>3)^7] & (1<<(nr&7))) != 0;
|
||||
}
|
||||
|
||||
struct list_head
|
||||
{
|
||||
struct list_head *next, *prev;
|
||||
};
|
||||
|
||||
static inline void
|
||||
__list_del (struct list_head *prev, struct list_head *next)
|
||||
{
|
||||
next->prev = prev;
|
||||
prev->next = next;
|
||||
}
|
||||
|
||||
static inline void
|
||||
list_del (struct list_head *entry)
|
||||
{
|
||||
__list_del(entry->prev, entry->next);
|
||||
entry->next = 0;
|
||||
entry->prev = 0;
|
||||
}
|
||||
|
||||
extern int nr_active_pages;
|
||||
extern int nr_inactive_pages;
|
||||
extern struct list_head active_list;
|
||||
|
||||
typedef struct page
|
||||
{
|
||||
unsigned long flags;
|
||||
struct list_head lru;
|
||||
} mem_map_t;
|
||||
|
||||
void
|
||||
activate_page_nolock (struct page * page)
|
||||
{
|
||||
if ((__builtin_constant_p((6))
|
||||
? __constant_test_bit((6),(&(page)->flags))
|
||||
: __test_bit((6),(&(page)->flags)) )
|
||||
&& !(__builtin_constant_p((7))
|
||||
? __constant_test_bit((7),(&(page)->flags))
|
||||
: __test_bit((7),(&(page)->flags)) ))
|
||||
{
|
||||
list_del(&(page)->lru);
|
||||
nr_inactive_pages--;
|
||||
if (!(__builtin_constant_p(6) ? __constant_test_bit((6),(&(page)->flags))
|
||||
: __test_bit((6),(&(page)->flags))))
|
||||
printk("", "", 43);
|
||||
|
||||
if ((__builtin_constant_p(7) ? __constant_test_bit((7),(&(page)->flags))
|
||||
: __test_bit((7),(&(page)->flags))))
|
||||
printk("", "", 43);
|
||||
|
||||
(__builtin_constant_p(7) ? __constant_set_bit((7),(&(page)->flags))
|
||||
: __set_bit((7),(&(page)->flags)) );
|
||||
list_add(&(page)->lru, &active_list);
|
||||
nr_active_pages++;
|
||||
}
|
||||
}
|
||||
107
gcc/testsuite/gcc.target/sh/pr51244-14.c
Normal file
107
gcc/testsuite/gcc.target/sh/pr51244-14.c
Normal file
@ -0,0 +1,107 @@
|
||||
/* This is a case extracted from CSiBE which would sometimes contain the
|
||||
following sequence:
|
||||
cmp/eq r12,r13
|
||||
movt r0
|
||||
xor #1,r0
|
||||
extu.b r0,r0
|
||||
movt r3
|
||||
tst r0,r0
|
||||
bf/s .L35
|
||||
where the negated T bit store did not combine properly. Since there are
|
||||
other movt insns we only check for the xor and the extu. */
|
||||
/* { dg-do compile { target "sh*-*-*" } } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
|
||||
/* { dg-final { scan-assembler-not "xor|extu" } } */
|
||||
|
||||
typedef struct transaction_s transaction_t;
|
||||
|
||||
struct journal_head
|
||||
{
|
||||
transaction_t * b_transaction;
|
||||
struct journal_head *b_cpnext, *b_cpprev;
|
||||
};
|
||||
|
||||
struct transaction_s
|
||||
{
|
||||
struct journal_head * t_checkpoint_list;
|
||||
transaction_t *t_cpnext, *t_cpprev;
|
||||
};
|
||||
|
||||
struct journal_s
|
||||
{
|
||||
transaction_t * j_checkpoint_transactions;
|
||||
unsigned long j_first, j_last;
|
||||
};
|
||||
|
||||
typedef struct journal_s journal_t;
|
||||
|
||||
extern int __try_to_free_cp_buf (struct journal_head *jh);
|
||||
extern int __cleanup_transaction (journal_t *journal, transaction_t *transaction);
|
||||
extern void __flush_batch (void **bhs, int *batch_count);
|
||||
extern void* jh2bh (void*);
|
||||
|
||||
static int
|
||||
__flush_buffer (journal_t *journal, struct journal_head *jh,
|
||||
void **bhs, int *batch_count, int *drop_count)
|
||||
{
|
||||
void *bh = jh2bh (jh);
|
||||
int ret = 0;
|
||||
if (bh)
|
||||
{
|
||||
bhs[*batch_count] = bh;
|
||||
(*batch_count)++;
|
||||
if (*batch_count == 64)
|
||||
ret = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
int last_buffer = 0;
|
||||
if (jh->b_cpnext == jh)
|
||||
last_buffer = 1;
|
||||
if (__try_to_free_cp_buf (jh))
|
||||
{
|
||||
(*drop_count)++;
|
||||
ret = last_buffer;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
log_do_checkpoint (journal_t *journal, int nblocks)
|
||||
{
|
||||
transaction_t *transaction, *last_transaction, *next_transaction;
|
||||
int batch_count = 0;
|
||||
void *bhs[64];
|
||||
|
||||
repeat:
|
||||
transaction = journal->j_checkpoint_transactions;
|
||||
if (transaction == ((void *)0))
|
||||
return 0;
|
||||
last_transaction = transaction->t_cpprev;
|
||||
next_transaction = transaction;
|
||||
do
|
||||
{
|
||||
struct journal_head *jh, *last_jh, *next_jh;
|
||||
int drop_count = 0;
|
||||
int cleanup_ret, retry = 0;
|
||||
transaction = next_transaction;
|
||||
next_transaction = transaction->t_cpnext;
|
||||
jh = transaction->t_checkpoint_list;
|
||||
last_jh = jh->b_cpprev;
|
||||
next_jh = jh;
|
||||
do
|
||||
{
|
||||
jh = next_jh;
|
||||
next_jh = jh->b_cpnext;
|
||||
retry = __flush_buffer(journal, jh, bhs, &batch_count, &drop_count);
|
||||
} while (jh != last_jh && !retry);
|
||||
|
||||
if (retry)
|
||||
goto repeat;
|
||||
|
||||
cleanup_ret = __cleanup_transaction(journal, transaction);
|
||||
goto repeat;
|
||||
} while (transaction != last_transaction);
|
||||
}
|
||||
71
gcc/testsuite/gcc.target/sh/pr51244-15.c
Normal file
71
gcc/testsuite/gcc.target/sh/pr51244-15.c
Normal file
@ -0,0 +1,71 @@
|
||||
/* Check that the redundant test removal code in the *cbranch_t split works
|
||||
as expected on non-SH2A targets. Because on SH2A the movrt instruction
|
||||
is used, this test is re-used and checked differently in pr51244-16.c. */
|
||||
/* { dg-do compile { target "sh*-*-*" } } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
|
||||
/* { dg-final { scan-assembler-times "tst" 6 } } */
|
||||
/* { dg-final { scan-assembler-times "movt" 6 } } */
|
||||
/* { dg-final { scan-assembler-times "xor" 3 } } */
|
||||
/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
|
||||
|
||||
typedef char bool;
|
||||
|
||||
int
|
||||
test_0 (int a, int b, int c, int* d)
|
||||
{
|
||||
/* non SH2A: 1x tst, 1x movt, 1x xor
|
||||
SH2A: 1x tst, 1x movrt */
|
||||
bool x = a == 0;
|
||||
d[2] = !x;
|
||||
return x ? b : c;
|
||||
}
|
||||
|
||||
int
|
||||
test_1 (int a, int b, int c, int* d)
|
||||
{
|
||||
/* 1x tst, 1x movt */
|
||||
bool x = a != 0;
|
||||
d[2] = !x;
|
||||
return x ? b : c;
|
||||
}
|
||||
|
||||
int
|
||||
test_2 (int a, int b, int c, char* d)
|
||||
{
|
||||
/* Check that there is no sign/zero-extension before the store.
|
||||
non SH2A: 1x tst, 1x movt, 1x xor
|
||||
SH2A: 1x tst, 1x movrt */
|
||||
bool x = a == 0;
|
||||
d[2] = !x;
|
||||
return x ? b : c;
|
||||
}
|
||||
|
||||
int
|
||||
test_3 (int a, int b, int c, char* d)
|
||||
{
|
||||
/* Check that there is no sign/zero-extension before the store.
|
||||
1x tst, 1x movt */
|
||||
bool x = a != 0;
|
||||
d[2] = !x;
|
||||
return x ? b : c;
|
||||
}
|
||||
|
||||
int
|
||||
test_4 (int a, int b, int c, char* d)
|
||||
{
|
||||
/* 1x tst, 1x movt */
|
||||
bool x = a != 0;
|
||||
d[2] = !x;
|
||||
return !x ? b : c;
|
||||
}
|
||||
|
||||
int
|
||||
test_5 (int a, int b, int c, char* d)
|
||||
{
|
||||
/* non SH2A: 1x tst, 1x movt, 1x xor
|
||||
SH2A: 1x tst, 1x movrt */
|
||||
bool x = a == 0;
|
||||
d[2] = !x;
|
||||
return !x ? b : c;
|
||||
}
|
||||
11
gcc/testsuite/gcc.target/sh/pr51244-16.c
Normal file
11
gcc/testsuite/gcc.target/sh/pr51244-16.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* Check that the redundant test removal code in the *cbranch_t split works
|
||||
as expected on SH2A targets. */
|
||||
/* { dg-do compile { target "sh*-*-*" } } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
|
||||
/* { dg-final { scan-assembler-times "tst" 6 } } */
|
||||
/* { dg-final { scan-assembler-times "movt" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "movrt" 3 } } */
|
||||
/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
|
||||
|
||||
#include "pr51244-15.c"
|
||||
Loading…
Reference in New Issue
Block a user