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i386-common.c (OPTION_MASK_ISA_AVX512BW_SET): Define.

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gcc/
        * common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX512BW_SET) : Define.
	(OPTION_MASK_ISA_AVX512BW_UNSET): Ditto.
	(OPTION_MASK_ISA_AVX512VL_UNSET) : Ditto.
	(ix86_handle_option): Handle OPT_mavx512bw.
	* config/i386/cpuid.h (bit_AVX512BW): Define.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512bw,
	set -mavx512bw accordingly.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	OPTION_MASK_ISA_AVX512BW.
	* config/i386/i386.c (ix86_target_string): Handle -mavx512bw.
	(ix86_option_override_internal): Define PTA_AVX512BW, handle
	PTA_AVX512BW and OPTION_MASK_ISA_AVX512BW.
	(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512bw.
	* config/i386/i386.h (TARGET_AVX512BW): Define.
	(TARGET_AVX512BW_P(x)): Ditto.
	* config/i386/i386.opt: Add mavx512bw.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r213811
This commit is contained in:
Alexander Ivchenko 2014-08-11 11:22:26 +00:00 committed by Kirill Yukhin
parent 5f732aeb8e
commit b525d9437f
8 changed files with 64 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
gcc/ChangeLog
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@ -1,3 +1,30 @@
2014-08-11 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX512BW_SET) : Define.
(OPTION_MASK_ISA_AVX512BW_UNSET): Ditto.
(OPTION_MASK_ISA_AVX512VL_UNSET) : Ditto.
(ix86_handle_option): Handle OPT_mavx512bw.
* config/i386/cpuid.h (bit_AVX512BW): Define.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512bw,
set -mavx512bw accordingly.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
OPTION_MASK_ISA_AVX512BW.
* config/i386/i386.c (ix86_target_string): Handle -mavx512bw.
(ix86_option_override_internal): Define PTA_AVX512BW, handle
PTA_AVX512BW and OPTION_MASK_ISA_AVX512BW.
(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512bw.
* config/i386/i386.h (TARGET_AVX512BW): Define.
(TARGET_AVX512BW_P(x)): Ditto.
* config/i386/i386.opt: Add mavx512bw.
2014-08-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/62070

19
gcc/common/config/i386/i386-common.c
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@ -67,6 +67,8 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512DQ_SET \
(OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512BW_SET \
(OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
@ -154,11 +156,13 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
#define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET)
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
| OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET)
#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
#define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW
#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
@ -409,6 +413,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
case OPT_mavx512bw:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
}
return true;
case OPT_mfma:
if (value)
{

1
gcc/config/i386/cpuid.h
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@ -81,6 +81,7 @@
#define bit_AVX512ER (1 << 27)
#define bit_AVX512CD (1 << 28)
#define bit_SHA (1 << 29)
#define bit_AVX512BW (1 << 30)
/* %ecx */
#define bit_PREFETCHWT1 (1 << 0)

6
gcc/config/i386/driver-i386.c
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@ -411,7 +411,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
unsigned int has_avx512dq = 0;
unsigned int has_avx512dq = 0, has_avx512bw = 0;
bool arch;
@ -491,6 +491,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
has_sha = ebx & bit_SHA;
has_clflushopt = ebx & bit_CLFLUSHOPT;
has_avx512dq = ebx & bit_AVX512DQ;
has_avx512bw = ebx & bit_AVX512BW;
has_prefetchwt1 = ecx & bit_PREFETCHWT1;
}
@ -904,6 +905,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
sse4a, cx16, sahf, movbe, aes, sha, pclmul,
@ -912,7 +914,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
fxsr, xsave, xsaveopt, avx512f, avx512er,
avx512cd, avx512pf, prefetchwt1, clflushopt,
xsavec, xsaves, avx512dq, NULL);
xsavec, xsaves, avx512dq, avx512bw, NULL);
}
done:

2
gcc/config/i386/i386-c.c
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@ -347,6 +347,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX512PF__");
if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
def_or_undef (parse_in, "__AVX512DQ__");
if (isa_flag & OPTION_MASK_ISA_AVX512BW)
def_or_undef (parse_in, "__AVX512BW__");
if (isa_flag & OPTION_MASK_ISA_FMA)
def_or_undef (parse_in, "__FMA__");
if (isa_flag & OPTION_MASK_ISA_RTM)

6
gcc/config/i386/i386.c
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@ -2593,6 +2593,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
{ "-mavx512cd", OPTION_MASK_ISA_AVX512CD },
{ "-mavx512pf", OPTION_MASK_ISA_AVX512PF },
{ "-mavx512dq", OPTION_MASK_ISA_AVX512DQ },
{ "-mavx512bw", OPTION_MASK_ISA_AVX512BW },
{ "-msse4a", OPTION_MASK_ISA_SSE4A },
{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
@ -3124,6 +3125,7 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
#define PTA_CORE2 \
(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
@ -3694,6 +3696,9 @@ ix86_option_override_internal (bool main_args_p,
if (processor_alias_table[i].flags & PTA_AVX512DQ
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
if (processor_alias_table[i].flags & PTA_AVX512BW
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
@ -4551,6 +4556,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
IX86_ATTR_ISA ("avx512er", OPT_mavx512er),
IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd),
IX86_ATTR_ISA ("avx512dq", OPT_mavx512dq),
IX86_ATTR_ISA ("avx512bw", OPT_mavx512bw),
IX86_ATTR_ISA ("mmx", OPT_mmmx),
IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),

2
gcc/config/i386/i386.h
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@ -73,6 +73,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ
#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
#define TARGET_AVX512BW TARGET_ISA_AVX512BW
#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x)
#define TARGET_FMA TARGET_ISA_FMA
#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
#define TARGET_SSE4A TARGET_ISA_SSE4A

4
gcc/config/i386/i386.opt
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@ -645,6 +645,10 @@ mavx512dq
Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation
mavx512bw
Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation
mfma
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation