rl78-real.md (bf): New pattern.
* config/rl78/rl78-real.md (bf): New pattern. (bt): New pattern. * config/rl78/rl78.c (rl78_print_operand_1): Handle %B. (rl78_print_operand): Do not put a # before a %B. * config/rl78/rl78.opt: Tweak doc strings. From-SVN: r202676
This commit is contained in:
Nick Clifton
DJ Delorie
parent
05eac2ce91
commit
b5ba3a9b55
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@ -1,3 +1,11 @@
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2013-09-17 Nick Clifton <nickc@redhat.com>
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* config/rl78/rl78-real.md (bf): New pattern.
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(bt): New pattern.
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* config/rl78/rl78.c (rl78_print_operand_1): Handle %B.
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(rl78_print_operand): Do not put a # before a %B.
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* config/rl78/rl78.opt: Tweak doc strings.
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2013-09-17 DJ Delorie <dj@redhat.com>
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* config/rl78/constraints.md (Wcv): Allow up to $r31.
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@ -459,3 +459,58 @@
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[(set (match_dup 0) (reg:HI AX_REG))]
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)
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;; Bit test and branch insns.
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;; NOTE: These patterns will work for bits in other places, not just A.
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(define_insn "bf"
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[(set (pc)
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(if_then_else (eq (and (reg:QI A_REG)
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(match_operand 0 "immediate_operand" "n"))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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"bf\tA.%B0, $%1"
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)
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(define_insn "bt"
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[(set (pc)
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(if_then_else (ne (and (reg:QI A_REG)
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(match_operand 0 "immediate_operand" "n"))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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"bt\tA.%B0, $%1"
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)
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;; NOTE: These peepholes are fragile. They rely upon GCC generating
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;; a specific sequence on insns, based upon examination of test code.
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;; Improvements to GCC or using code other than the test code can result
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;; in the peephole not matching and the optimization being missed.
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(define_peephole2
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[(set (match_operand:QI 1 "register_operand") (reg:QI A_REG))
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(set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand")))
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(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
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(label_ref (match_operand 3 ""))
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(pc)))]
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"peep2_regno_dead_p (3, REGNO (operands[1]))
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&& exact_log2 (INTVAL (operands[2])) >= 0"
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[(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 2)) (const_int 0))
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(label_ref (match_dup 3)) (pc)))]
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)
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(define_peephole2
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[(set (match_operand:QI 1 "register_operand") (reg:QI A_REG))
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(set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand")))
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(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
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(label_ref (match_operand 3 ""))
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(pc)))]
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"peep2_regno_dead_p (3, REGNO (operands[1]))
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&& exact_log2 (INTVAL (operands[2])) >= 0"
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[(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 2)) (const_int 0))
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(label_ref (match_dup 3)) (pc)))]
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)
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@ -1286,6 +1286,7 @@ rl78_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
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s - shift count mod 8
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S - shift count mod 16
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r - reverse shift count (8-(count mod 8))
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B - bit position
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h - bottom HI of an SI
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H - top HI of an SI
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@ -1412,6 +1413,8 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
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fprintf (file, "%ld", INTVAL (op) & 0xffff);
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else if (letter == 'e')
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fprintf (file, "%ld", (INTVAL (op) >> 16) & 0xff);
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else if (letter == 'B')
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fprintf (file, "%d", exact_log2 (INTVAL (op)));
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else if (letter == 'E')
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fprintf (file, "%ld", (INTVAL (op) >> 24) & 0xff);
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else if (letter == 'm')
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@ -1605,7 +1608,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
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static void
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rl78_print_operand (FILE * file, rtx op, int letter)
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{
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if (CONSTANT_P (op) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S')
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if (CONSTANT_P (op) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S' && letter != 'B')
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fprintf (file, "#");
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rl78_print_operand_1 (file, op, letter);
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}
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@ -23,7 +23,7 @@ HeaderInclude
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config/rl78/rl78-opts.h
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msim
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Target
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Target Report
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Use the simulator runtime.
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mmul=
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@ -43,13 +43,13 @@ EnumValue
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Enum(rl78_mul_types) String(g13) Value(MUL_G13)
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mallregs
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Target Mask(ALLREGS)
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Target Mask(ALLREGS) Report Optimization
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Use all registers, reserving none for interrupt handlers.
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mrelax
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Target
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Enable assembler and linker relaxation.
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Target Report Optimization
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Enable assembler and linker relaxation. Enabled by default at -Os.
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mg10
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Target Mask(G10)
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Target Mask(G10) Report
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Target the RL78/G10 series
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