rs6000.c (scc_comparison_operator): Make equivalent to branch_positive_comparison_operator.
* config/rs6000/rs6000.c (scc_comparison_operator): Make equivalent to branch_positive_comparison_operator. (ccr_bit): Check that sCOND conditions are actually a positive bit. (print_operand): Remove %D substitution. (rs6000_emit_sCOND): Generate complement operation to ensure that sCOND input is a positive bit. * config/rs6000/rs6000.md: Rearrange sCOND templates to be in the same order as bCOND, and add the missing ones. Remove the %D substitutions from the scc patterns. From-SVN: r66441
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
parent
8d90f9c029
commit
b7053a3fde
@ -1,5 +1,15 @@
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2003-05-03 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000.c (scc_comparison_operator): Make equivalent
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to branch_positive_comparison_operator.
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(ccr_bit): Check that sCOND conditions are actually a positive bit.
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(print_operand): Remove %D substitution.
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(rs6000_emit_sCOND): Generate complement operation to ensure that
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sCOND input is a positive bit.
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* config/rs6000/rs6000.md: Rearrange sCOND templates to be in the
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same order as bCOND, and add the missing ones. Remove the %D
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substitutions from the scc patterns.
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* simplify-rtx.c (simplify_relational_operation): Add case for
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! (fabs(x) < 0.0).
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@ -7049,34 +7049,15 @@ branch_positive_comparison_operator (op, mode)
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|| code == UNORDERED);
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}
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/* Return 1 if OP is a comparison operation that is valid for an scc insn.
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We check the opcode against the mode of the CC value and disallow EQ or
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NE comparisons for integers. */
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/* Return 1 if OP is a comparison operation that is valid for an scc
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insn: it must be a positive comparison. */
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int
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scc_comparison_operator (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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enum rtx_code code = GET_CODE (op);
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enum machine_mode cc_mode;
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if (GET_MODE (op) != mode && mode != VOIDmode)
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return 0;
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if (GET_RTX_CLASS (code) != '<')
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return 0;
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cc_mode = GET_MODE (XEXP (op, 0));
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if (GET_MODE_CLASS (cc_mode) != MODE_CC)
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return 0;
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validate_condition_mode (code, cc_mode);
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if (code == NE && cc_mode != CCFPmode)
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return 0;
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return 1;
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return branch_positive_comparison_operator (op, mode);
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}
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int
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@ -7501,6 +7482,12 @@ ccr_bit (op, scc_p)
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validate_condition_mode (code, cc_mode);
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/* When generating a sCOND operation, only positive conditions are
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allowed. */
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if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
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&& code != GTU && code != LTU)
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abort ();
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switch (code)
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{
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case NE:
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@ -7697,42 +7684,6 @@ print_operand (file, x, code)
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/* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
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output_operand. */
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case 'D':
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/* There used to be a comment for 'C' reading "This is an
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optional cror needed for certain floating-point
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comparisons. Otherwise write nothing." */
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/* Similar, except that this is for an scc, so we must be able to
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encode the test in a single bit that is one. We do the above
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for any LE, GE, GEU, or LEU and invert the bit for NE. */
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if (GET_CODE (x) == LE || GET_CODE (x) == GE
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|| GET_CODE (x) == LEU || GET_CODE (x) == GEU)
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{
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int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
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fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
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base_bit + 2,
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base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
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}
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else if (GET_CODE (x) == NE)
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{
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int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
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fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
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base_bit + 2, base_bit + 2);
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}
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else if (TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT
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&& GET_CODE (x) == EQ
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&& GET_MODE (XEXP (x, 0)) == CCFPmode)
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{
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int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
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fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 1,
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base_bit + 1, base_bit + 1);
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}
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return;
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case 'E':
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/* X is a CR register. Print the number of the EQ bit of the CR */
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if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
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@ -8686,8 +8637,28 @@ rs6000_emit_sCOND (code, result)
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{
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rtx condition_rtx;
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enum machine_mode op_mode;
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enum rtx_code cond_code;
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condition_rtx = rs6000_generate_compare (code);
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cond_code = GET_CODE (condition_rtx);
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if (cond_code == NE
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|| cond_code == GE || cond_code == LE
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|| cond_code == GEU || cond_code == LEU
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|| cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
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{
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rtx not_result = gen_reg_rtx (CCEQmode);
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rtx not_op, rev_cond_rtx;
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enum machine_mode cc_mode;
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cc_mode = GET_MODE (XEXP (condition_rtx, 0));
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rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code),
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SImode, XEXP (condition_rtx, 0), const0_rtx);
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not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
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emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
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condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
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}
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op_mode = GET_MODE (rs6000_compare_op0);
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if (op_mode == VOIDmode)
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@ -10919,34 +10919,6 @@
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DONE;
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}")
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;; A > 0 is best done using the portable sequence, so fail in that case.
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(define_expand "sgt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"
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{
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if (! rs6000_compare_fp_p
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&& (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
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FAIL;
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rs6000_emit_sCOND (GT, operands[0]);
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DONE;
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}")
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;; A < 0 is best done in the portable way for A an integer.
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(define_expand "slt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"
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{
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if (! rs6000_compare_fp_p
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&& (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
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FAIL;
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rs6000_emit_sCOND (LT, operands[0]);
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DONE;
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}")
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;; A >= 0 is best done the portable way for A an integer.
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(define_expand "sge"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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@ -10961,6 +10933,20 @@
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DONE;
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}")
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;; A > 0 is best done using the portable sequence, so fail in that case.
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(define_expand "sgt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"
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{
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if (! rs6000_compare_fp_p
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&& (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
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FAIL;
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rs6000_emit_sCOND (GT, operands[0]);
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DONE;
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}")
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;; A <= 0 is best done the portable way for A an integer.
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(define_expand "sle"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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@ -10975,25 +10961,80 @@
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DONE;
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}")
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(define_expand "sgtu"
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;; A < 0 is best done in the portable way for A an integer.
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(define_expand "slt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
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"
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{
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if (! rs6000_compare_fp_p
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&& (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
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FAIL;
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(define_expand "sltu"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
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rs6000_emit_sCOND (LT, operands[0]);
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DONE;
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}")
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(define_expand "sgeu"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
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(define_expand "sgtu"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
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(define_expand "sleu"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
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(define_expand "sltu"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
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(define_expand "sunordered"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
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(define_expand "sordered"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
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(define_expand "suneq"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
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(define_expand "sunge"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
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(define_expand "sungt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
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(define_expand "sunle"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
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(define_expand "sunlt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
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(define_expand "sltgt"
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[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
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""
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"{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
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;; Here are the actual compare insns.
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(define_insn "*cmpsi_internal1"
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@ -11141,7 +11182,7 @@
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[(match_operand 2 "cc_reg_operand" "y")
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(const_int 0)]))]
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""
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"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set_attr "type" "mfcr")
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(set_attr "length" "12")])
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@ -11150,7 +11191,7 @@
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
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"TARGET_ISEL"
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"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
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[(set_attr "type" "mfcr")
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(set_attr "length" "12")])
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@ -11160,7 +11201,7 @@
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[(match_operand 2 "cc_reg_operand" "y")
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(const_int 0)]))]
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"TARGET_POWERPC64"
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"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set_attr "type" "mfcr")
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(set_attr "length" "12")])
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@ -11174,7 +11215,7 @@
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(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
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"! TARGET_POWERPC64"
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"@
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%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
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mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
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#"
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[(set_attr "type" "delayed_compare")
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(set_attr "length" "12,16")])
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@ -11216,7 +11257,7 @@
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operands[4] = GEN_INT (count);
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operands[5] = GEN_INT (put_bit);
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return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
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return \"mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
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}"
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[(set_attr "type" "mfcr")
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(set_attr "length" "12")])
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@ -11251,7 +11292,7 @@
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operands[5] = GEN_INT (count);
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operands[6] = GEN_INT (put_bit);
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return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
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return \"mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
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}"
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[(set_attr "type" "delayed_compare")
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(set_attr "length" "12,16")])
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@ -11289,7 +11330,7 @@
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[(match_operand 5 "cc_reg_operand" "y")
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(const_int 0)]))]
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"REGNO (operands[2]) != REGNO (operands[5])"
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"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
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"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
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[(set_attr "type" "mfcr")
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(set_attr "length" "20")])
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@ -11303,7 +11344,7 @@
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[(match_operand 5 "cc_reg_operand" "y")
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(const_int 0)]))]
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"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
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"%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
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"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
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[(set_attr "type" "mfcr")
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(set_attr "length" "20")])
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