i386.c (ix86_builtin_vectorization_cost): Do not feed width-specific load/store costs through ix86_vec_cost.
2018-10-18 Richard Biener <rguenther@suse.de> * config/i386/i386.c (ix86_builtin_vectorization_cost): Do not feed width-specific load/store costs through ix86_vec_cost. * config/i386/x86-tune-costs.h (athlon_cost): Adjust. (k8_cost): Likewise. (bdver_cost): Likewise. (znver1_cost): Likewise. (btver1_cost): Likewise. (btver2_cost): Likewise. From-SVN: r265268
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Richard Biener
Richard Biener
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@ -1,3 +1,14 @@
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2018-10-18 Richard Biener <rguenther@suse.de>
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* config/i386/i386.c (ix86_builtin_vectorization_cost): Do not
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feed width-specific load/store costs through ix86_vec_cost.
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* config/i386/x86-tune-costs.h (athlon_cost): Adjust.
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(k8_cost): Likewise.
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(bdver_cost): Likewise.
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(znver1_cost): Likewise.
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(btver1_cost): Likewise.
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(btver2_cost): Likewise.
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2018-10-18 H.J. Lu <hongjiu.lu@intel.com>
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* simplify-rtx.c (simplify_subreg): Call simplify_gen_subreg
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@ -45108,16 +45108,14 @@ ix86_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
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/* See PR82713 - we may end up being called on non-vector type. */
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if (index < 0)
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index = 2;
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return ix86_vec_cost (mode,
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COSTS_N_INSNS (ix86_cost->sse_load[index]) / 2);
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return COSTS_N_INSNS (ix86_cost->sse_load[index]) / 2;
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case vector_store:
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index = sse_store_index (mode);
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/* See PR82713 - we may end up being called on non-vector type. */
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if (index < 0)
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index = 2;
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return ix86_vec_cost (mode,
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COSTS_N_INSNS (ix86_cost->sse_store[index]) / 2);
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return COSTS_N_INSNS (ix86_cost->sse_store[index]) / 2;
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case vec_to_scalar:
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case scalar_to_vec:
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@ -45130,18 +45128,14 @@ ix86_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
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/* See PR82713 - we may end up being called on non-vector type. */
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if (index < 0)
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index = 2;
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return ix86_vec_cost (mode,
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COSTS_N_INSNS
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(ix86_cost->sse_unaligned_load[index]) / 2);
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return COSTS_N_INSNS (ix86_cost->sse_unaligned_load[index]) / 2;
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case unaligned_store:
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index = sse_store_index (mode);
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/* See PR82713 - we may end up being called on non-vector type. */
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if (index < 0)
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index = 2;
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return ix86_vec_cost (mode,
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COSTS_N_INSNS
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(ix86_cost->sse_unaligned_store[index]) / 2);
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return COSTS_N_INSNS (ix86_cost->sse_unaligned_store[index]) / 2;
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case vector_gather_load:
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return ix86_vec_cost (mode,
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@ -795,12 +795,12 @@ struct processor_costs athlon_cost = {
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{4, 4}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{4, 4, 6, 12, 24}, /* cost of loading SSE registers
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{4, 4, 12, 12, 24}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{4, 4, 6, 12, 24}, /* cost of unaligned loads. */
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{4, 4, 5, 10, 20}, /* cost of storing SSE registers
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{4, 4, 12, 12, 24}, /* cost of unaligned loads. */
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{4, 4, 10, 10, 20}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{4, 4, 5, 10, 20}, /* cost of unaligned stores. */
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{4, 4, 10, 10, 20}, /* cost of unaligned stores. */
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5, 5, /* SSE->integer and integer->SSE moves */
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4, 4, /* Gather load static, per_elt. */
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4, 4, /* Gather store static, per_elt. */
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@ -891,12 +891,12 @@ struct processor_costs k8_cost = {
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{4, 4}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{4, 3, 6, 12, 24}, /* cost of loading SSE registers
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{4, 3, 12, 12, 24}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{4, 3, 6, 12, 24}, /* cost of unaligned loads. */
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{4, 4, 5, 10, 20}, /* cost of storing SSE registers
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{4, 3, 12, 12, 24}, /* cost of unaligned loads. */
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{4, 4, 10, 10, 20}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{4, 4, 5, 10, 20}, /* cost of unaligned stores. */
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{4, 4, 10, 10, 20}, /* cost of unaligned stores. */
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5, 5, /* SSE->integer and integer->SSE moves */
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4, 4, /* Gather load static, per_elt. */
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4, 4, /* Gather store static, per_elt. */
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@ -1100,12 +1100,12 @@ const struct processor_costs bdver_cost = {
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{10, 10}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{12, 12, 10, 20, 30}, /* cost of loading SSE registers
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{12, 12, 10, 40, 60}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{12, 12, 10, 20, 30}, /* cost of unaligned loads. */
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{10, 10, 10, 20, 30}, /* cost of storing SSE registers
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{12, 12, 10, 40, 60}, /* cost of unaligned loads. */
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{10, 10, 10, 40, 60}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 10, 20, 30}, /* cost of unaligned stores. */
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{10, 10, 10, 40, 60}, /* cost of unaligned stores. */
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16, 20, /* SSE->integer and integer->SSE moves */
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12, 12, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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@ -1212,12 +1212,12 @@ struct processor_costs znver1_cost = {
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{8, 8}, /* cost of storing MMX registers
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in SImode and DImode. */
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2, 3, 6, /* cost of moving XMM,YMM,ZMM register. */
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{6, 6, 6, 6, 12}, /* cost of loading SSE registers
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{6, 6, 6, 12, 24}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit. */
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{6, 6, 6, 6, 12}, /* cost of unaligned loads. */
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{8, 8, 8, 8, 16}, /* cost of storing SSE registers
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{6, 6, 6, 12, 24}, /* cost of unaligned loads. */
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{8, 8, 8, 16, 32}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit. */
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{8, 8, 8, 8, 16}, /* cost of unaligned stores. */
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{8, 8, 8, 16, 32}, /* cost of unaligned stores. */
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6, 6, /* SSE->integer and integer->SSE moves. */
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/* VGATHERDPD is 23 uops and throughput is 9, VGATHERDPD is 35 uops,
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throughput 12. Approx 9 uops do not depend on vector size and every load
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@ -1420,12 +1420,12 @@ const struct processor_costs btver1_cost = {
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{12, 12}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{10, 10, 12, 24, 48}, /* cost of loading SSE registers
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{10, 10, 12, 48, 96}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 12, 24, 48}, /* cost of unaligned loads. */
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{10, 10, 12, 24, 48}, /* cost of storing SSE registers
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{10, 10, 12, 48, 96}, /* cost of unaligned loads. */
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{10, 10, 12, 48, 96}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 12, 24, 48}, /* cost of unaligned stores. */
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{10, 10, 12, 48, 96}, /* cost of unaligned stores. */
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14, 14, /* SSE->integer and integer->SSE moves */
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10, 10, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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@ -1511,12 +1511,12 @@ const struct processor_costs btver2_cost = {
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{12, 12}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{10, 10, 12, 24, 48}, /* cost of loading SSE registers
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{10, 10, 12, 48, 96}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 12, 24, 48}, /* cost of unaligned loads. */
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{10, 10, 12, 24, 48}, /* cost of storing SSE registers
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{10, 10, 12, 48, 96}, /* cost of unaligned loads. */
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{10, 10, 12, 48, 96}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 12, 24, 48}, /* cost of unaligned stores. */
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{10, 10, 12, 48, 96}, /* cost of unaligned stores. */
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14, 14, /* SSE->integer and integer->SSE moves */
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10, 10, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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