parent
81c2dfb933
commit
b7342d25ed
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@ -1,3 +1,13 @@
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2013-06-04 Ian Bolton <ian.bolton@arm.com>
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* config/aarch64/aarch64.md (*mov<mode>_aarch64): Call
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into function to generate MOVI instruction.
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* config/aarch64/aarch64.c (aarch64_simd_container_mode):
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New function.
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(aarch64_preferred_simd_mode): Turn into wrapper.
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(aarch64_output_scalar_simd_mov_immediate): New function.
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* config/aarch64/aarch64-protos.h: Add prototype for above.
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2013-06-04 Ian Bolton <ian.bolton@arm.com>
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2013-06-04 Ian Bolton <ian.bolton@arm.com>
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* config/aarch64/aarch64.c (simd_immediate_info): Remove
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* config/aarch64/aarch64.c (simd_immediate_info): Remove
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@ -149,6 +149,7 @@ bool aarch64_legitimate_pic_operand_p (rtx);
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bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
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bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
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bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
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bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
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enum machine_mode);
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enum machine_mode);
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char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode);
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char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
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char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
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bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
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bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
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bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
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bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
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@ -5989,30 +5989,55 @@ aarch64_vector_mode_supported_p (enum machine_mode mode)
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return false;
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return false;
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}
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}
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/* Return quad mode as the preferred SIMD mode. */
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/* Return appropriate SIMD container
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for MODE within a vector of WIDTH bits. */
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static enum machine_mode
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aarch64_simd_container_mode (enum machine_mode mode, unsigned width)
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{
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gcc_assert (width == 64 || width == 128);
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if (TARGET_SIMD)
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{
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if (width == 128)
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switch (mode)
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{
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case DFmode:
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return V2DFmode;
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case SFmode:
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return V4SFmode;
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case SImode:
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return V4SImode;
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case HImode:
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return V8HImode;
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case QImode:
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return V16QImode;
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case DImode:
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return V2DImode;
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default:
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break;
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}
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else
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switch (mode)
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{
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case SFmode:
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return V2SFmode;
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case SImode:
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return V2SImode;
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case HImode:
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return V4HImode;
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case QImode:
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return V8QImode;
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default:
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break;
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}
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}
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return word_mode;
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}
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/* Return 128-bit container as the preferred SIMD mode for MODE. */
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static enum machine_mode
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static enum machine_mode
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aarch64_preferred_simd_mode (enum machine_mode mode)
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aarch64_preferred_simd_mode (enum machine_mode mode)
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{
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{
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if (TARGET_SIMD)
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return aarch64_simd_container_mode (mode, 128);
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switch (mode)
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{
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case DFmode:
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return V2DFmode;
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case SFmode:
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return V4SFmode;
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case SImode:
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return V4SImode;
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case HImode:
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return V8HImode;
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case QImode:
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return V16QImode;
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case DImode:
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return V2DImode;
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break;
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default:;
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}
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return word_mode;
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}
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}
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/* Return the bitmask of possible vector sizes for the vectorizer
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/* Return the bitmask of possible vector sizes for the vectorizer
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@ -7282,6 +7307,18 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
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return templ;
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return templ;
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}
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}
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char*
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aarch64_output_scalar_simd_mov_immediate (rtx immediate,
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enum machine_mode mode)
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{
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enum machine_mode vmode;
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gcc_assert (!VECTOR_MODE_P (mode));
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vmode = aarch64_simd_container_mode (mode, 64);
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rtx v_op = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (immediate));
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return aarch64_output_simd_mov_immediate (v_op, vmode, 64);
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}
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/* Split operands into moves from op[1] + op[2] into op[0]. */
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/* Split operands into moves from op[1] + op[2] into op[0]. */
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void
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void
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(match_operand:SHORT 1 "general_operand" " r,M,D<hq>,m, m,rZ,*w,*w, r,*w"))]
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(match_operand:SHORT 1 "general_operand" " r,M,D<hq>,m, m,rZ,*w,*w, r,*w"))]
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"(register_operand (operands[0], <MODE>mode)
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"(register_operand (operands[0], <MODE>mode)
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|| aarch64_reg_or_zero (operands[1], <MODE>mode))"
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|| aarch64_reg_or_zero (operands[1], <MODE>mode))"
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"@
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{
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mov\\t%w0, %w1
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switch (which_alternative)
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mov\\t%w0, %1
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{
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movi\\t%0.<Vallxd>, %1
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case 0:
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ldr<size>\\t%w0, %1
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return "mov\t%w0, %w1";
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ldr\\t%<size>0, %1
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case 1:
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str<size>\\t%w1, %0
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return "mov\t%w0, %1";
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str\\t%<size>1, %0
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case 2:
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umov\\t%w0, %1.<v>[0]
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return aarch64_output_scalar_simd_mov_immediate (operands[1],
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dup\\t%0.<Vallxd>, %w1
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<MODE>mode);
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dup\\t%0, %1.<v>[0]"
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case 3:
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return "ldr<size>\t%w0, %1";
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case 4:
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return "ldr\t%<size>0, %1";
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case 5:
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return "str<size>\t%w1, %0";
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case 6:
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return "str\t%<size>1, %0";
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case 7:
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return "umov\t%w0, %1.<v>[0]";
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case 8:
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return "dup\t%0.<Vallxd>, %w1";
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case 9:
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return "dup\t%0, %1.<v>[0]";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*")
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[(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*")
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(set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup")
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(set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup")
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(set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")
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(set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")
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@ -1,3 +1,7 @@
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2013-06-04 Ian Bolton <ian.bolton@arm.com>
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* gcc.target/aarch64/movi_1.c: New test.
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2013-06-04 Tobias Burnus <burnus@net-b.de>
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2013-06-04 Tobias Burnus <burnus@net-b.de>
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PR fortran/37336
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PR fortran/37336
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@ -0,0 +1,13 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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void
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dummy (short* b)
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{
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/* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */
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/* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */
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/* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */
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register short x asm ("h8") = 1024;
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asm volatile ("" : : "w" (x));
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*b = x;
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}
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Loading…
Reference in New Issue