MIPS: Update I6400 scheduler.
gcc/ChangeLog: 2018-06-12 Prachi Godbole <prachi.godbole@imgtec.com> * config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit. (i6400_gpmul): Add cpu_unit. (i6400_gpdiv): Likewise. (i6400_msa_add_d): Update reservations. (i6400_msa_int_add) Likewise. (i6400_msa_short_logic3) Likewise. (i6400_msa_short_logic2) Likewise. (i6400_msa_short_logic) Likewise. (i6400_msa_move) Likewise. (i6400_msa_cmp) Likewise. (i6400_msa_short_float2) Likewise. (i6400_msa_div_d) Likewise. (i6400_msa_long_logic1) Likewise. (i6400_msa_long_logic2) Likewise. (i6400_msa_mult) Likewise. (i6400_msa_long_float2) Likewise. (i6400_msa_long_float4) Likewise. (i6400_msa_long_float5) Likewise. (i6400_msa_long_float8) Likewise. (i6400_fpu_fadd): Include frint type. (i6400_fpu_store): New define_insn_reservation. (i6400_fpu_load): Likewise. (i6400_fpu_move): Likewise. (i6400_fpu_fcmp): Likewise. (i6400_fpu_fmadd): Likewise. (i6400_int_mult): Include imul3nc type and update reservation. (i6400_int_div): Include idiv3 type and update reservation. (i6400_int_load): Update to check type not move_type. (i6400_int_store): Likewise. (i6400_int_prefetch): Set zero latency. From-SVN: r261489
This commit is contained in:
Prachi Godbole
Robert Suchanek
parent
57d0f7c6d7
commit
b74161d05d
@ -1,3 +1,36 @@
|
||||
2018-06-12 Prachi Godbole <prachi.godbole@imgtec.com>
|
||||
|
||||
* config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit.
|
||||
(i6400_gpmul): Add cpu_unit.
|
||||
(i6400_gpdiv): Likewise.
|
||||
(i6400_msa_add_d): Update reservations.
|
||||
(i6400_msa_int_add) Likewise.
|
||||
(i6400_msa_short_logic3) Likewise.
|
||||
(i6400_msa_short_logic2) Likewise.
|
||||
(i6400_msa_short_logic) Likewise.
|
||||
(i6400_msa_move) Likewise.
|
||||
(i6400_msa_cmp) Likewise.
|
||||
(i6400_msa_short_float2) Likewise.
|
||||
(i6400_msa_div_d) Likewise.
|
||||
(i6400_msa_long_logic1) Likewise.
|
||||
(i6400_msa_long_logic2) Likewise.
|
||||
(i6400_msa_mult) Likewise.
|
||||
(i6400_msa_long_float2) Likewise.
|
||||
(i6400_msa_long_float4) Likewise.
|
||||
(i6400_msa_long_float5) Likewise.
|
||||
(i6400_msa_long_float8) Likewise.
|
||||
(i6400_fpu_fadd): Include frint type.
|
||||
(i6400_fpu_store): New define_insn_reservation.
|
||||
(i6400_fpu_load): Likewise.
|
||||
(i6400_fpu_move): Likewise.
|
||||
(i6400_fpu_fcmp): Likewise.
|
||||
(i6400_fpu_fmadd): Likewise.
|
||||
(i6400_int_mult): Include imul3nc type and update reservation.
|
||||
(i6400_int_div): Include idiv3 type and update reservation.
|
||||
(i6400_int_load): Update to check type not move_type.
|
||||
(i6400_int_store): Likewise.
|
||||
(i6400_int_prefetch): Set zero latency.
|
||||
|
||||
2018-06-12 Eric Botcazou <ebotcazou@adacore.com>
|
||||
|
||||
* gcc.c: Document new %@{...} sequence.
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
(define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe,
|
||||
i6400_fpu_long_pipe")
|
||||
|
||||
(define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe")
|
||||
(define_cpu_unit "i6400_gpmul, i6400_gpdiv" "i6400_mdu_pipe")
|
||||
(define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe")
|
||||
(define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe")
|
||||
|
||||
@ -50,49 +50,49 @@
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(and (eq_attr "mode" "!V2DI")
|
||||
(eq_attr "alu_type" "simd_add")))
|
||||
"i6400_fpu_short, i6400_fpu_intadd")
|
||||
"i6400_fpu_short+i6400_fpu_intadd*2")
|
||||
|
||||
;; add, hadd, sub, hsub, average, min, max, compare
|
||||
(define_insn_reservation "i6400_msa_int_add" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_int_arith"))
|
||||
"i6400_fpu_short, i6400_fpu_intadd")
|
||||
"i6400_fpu_short+i6400_fpu_intadd*2")
|
||||
|
||||
;; sat, pcnt
|
||||
(define_insn_reservation "i6400_msa_short_logic3" 3
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_sat,simd_pcnt"))
|
||||
"i6400_fpu_short, i6400_fpu_logic")
|
||||
"i6400_fpu_short+i6400_fpu_logic*2")
|
||||
|
||||
;; shifts, nloc, nlzc, bneg, bclr, shf
|
||||
(define_insn_reservation "i6400_msa_short_logic2" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_shift,simd_shf,simd_bit"))
|
||||
"i6400_fpu_short, i6400_fpu_logic")
|
||||
"i6400_fpu_short+i6400_fpu_logic*2")
|
||||
|
||||
;; and, or, xor, ilv, pck, fill, splat
|
||||
(define_insn_reservation "i6400_msa_short_logic" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_permute,simd_logic,simd_splat,simd_fill"))
|
||||
"i6400_fpu_short, i6400_fpu_logic")
|
||||
"i6400_fpu_short+i6400_fpu_logic*2")
|
||||
|
||||
;; move.v, ldi
|
||||
(define_insn_reservation "i6400_msa_move" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_move"))
|
||||
"i6400_fpu_short, i6400_fpu_logic")
|
||||
"i6400_fpu_short+i6400_fpu_logic*2")
|
||||
|
||||
;; Float compare New: CMP.cond.fmt
|
||||
(define_insn_reservation "i6400_msa_cmp" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_fcmp"))
|
||||
"i6400_fpu_short, i6400_fpu_cmp")
|
||||
"i6400_fpu_short+i6400_fpu_cmp*2")
|
||||
|
||||
;; Float min, max, class
|
||||
(define_insn_reservation "i6400_msa_short_float2" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_fminmax,simd_fclass"))
|
||||
"i6400_fpu_short, i6400_fpu_float")
|
||||
"i6400_fpu_short+i6400_fpu_float*2")
|
||||
|
||||
;; div.d, mod.d (non-pipelined)
|
||||
(define_insn_reservation "i6400_msa_div_d" 36
|
||||
@ -158,43 +158,43 @@
|
||||
(define_insn_reservation "i6400_msa_long_logic1" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_bitmov,simd_insert"))
|
||||
"i6400_fpu_long, i6400_fpu_logic_l")
|
||||
"i6400_fpu_long+i6400_fpu_logic_l*2")
|
||||
|
||||
;; binsl, binsr, vshf, sld
|
||||
(define_insn_reservation "i6400_msa_long_logic2" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_bitins,simd_sld"))
|
||||
"i6400_fpu_long, i6400_fpu_logic_l")
|
||||
"i6400_fpu_long+i6400_fpu_logic_l*2")
|
||||
|
||||
;; Vector mul, dotp, madd, msub
|
||||
(define_insn_reservation "i6400_msa_mult" 5
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_mul"))
|
||||
"i6400_fpu_long, i6400_fpu_mult")
|
||||
"i6400_fpu_long+i6400_fpu_mult*2")
|
||||
|
||||
;; Float flog2
|
||||
(define_insn_reservation "i6400_msa_long_float2" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_flog2"))
|
||||
"i6400_fpu_long, i6400_fpu_float_l")
|
||||
"i6400_fpu_long+i6400_fpu_float_l*2")
|
||||
|
||||
;; fadd, fsub
|
||||
(define_insn_reservation "i6400_msa_long_float4" 4
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_fadd,simd_fcvt"))
|
||||
"i6400_fpu_long, i6400_fpu_float_l")
|
||||
"i6400_fpu_long+i6400_fpu_float_l*2")
|
||||
|
||||
;; fmul, fexp2
|
||||
(define_insn_reservation "i6400_msa_long_float5" 5
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_fmul,simd_fexp2"))
|
||||
"i6400_fpu_long, i6400_fpu_float_l")
|
||||
"i6400_fpu_long+i6400_fpu_float_l*2")
|
||||
|
||||
;; fmadd, fmsub
|
||||
(define_insn_reservation "i6400_msa_long_float8" 8
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "simd_fmadd"))
|
||||
"i6400_fpu_long, i6400_fpu_float_l")
|
||||
"i6400_fpu_long+i6400_fpu_float_l*2")
|
||||
|
||||
;; fdiv.d
|
||||
(define_insn_reservation "i6400_msa_fdiv_df" 30
|
||||
@ -222,7 +222,7 @@
|
||||
;; fadd, fsub, fcvt
|
||||
(define_insn_reservation "i6400_fpu_fadd" 4
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "fadd, fcvt"))
|
||||
(eq_attr "type" "fadd, fcvt, frint"))
|
||||
"i6400_fpu_long, i6400_fpu_apu")
|
||||
|
||||
;; fmul
|
||||
@ -244,6 +244,36 @@
|
||||
(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
|
||||
"i6400_fpu_long+i6400_fpu_apu*22")
|
||||
|
||||
;; sdc1, swc1
|
||||
(define_insn_reservation "i6400_fpu_store" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "fpstore"))
|
||||
"i6400_agen_lsu")
|
||||
|
||||
;; ldc1, lwc1
|
||||
(define_insn_reservation "i6400_fpu_load" 3
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "fpload"))
|
||||
"i6400_agen_lsu")
|
||||
|
||||
;; mfc, mtc
|
||||
(define_insn_reservation "i6400_fpu_move" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "move_type" "mfc, mtc"))
|
||||
"i6400_control_alu0 | i6400_agen_alu1")
|
||||
|
||||
;; fcmp
|
||||
(define_insn_reservation "i6400_fpu_fcmp" 2
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "fcmp"))
|
||||
"i6400_fpu_short, i6400_fpu_apu")
|
||||
|
||||
;; fmadd
|
||||
(define_insn_reservation "i6400_fpu_fmadd" 8
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "fmadd"))
|
||||
"i6400_fpu_long, i6400_fpu_apu")
|
||||
|
||||
;;
|
||||
;; Integer pipe
|
||||
;;
|
||||
@ -272,32 +302,32 @@
|
||||
(eq_attr "type" "nop"))
|
||||
"nothing")
|
||||
|
||||
;; mult, multu, mul
|
||||
;; mul, mulu, muh, muhu
|
||||
(define_insn_reservation "i6400_int_mult" 4
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "imul3,imul"))
|
||||
"i6400_gpmuldiv")
|
||||
(eq_attr "type" "imul3,imul,imul3nc"))
|
||||
"i6400_gpmul")
|
||||
|
||||
;; divide
|
||||
(define_insn_reservation "i6400_int_div" 32
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "idiv"))
|
||||
"i6400_gpmuldiv*32")
|
||||
(eq_attr "type" "idiv,idiv3"))
|
||||
"i6400_gpdiv*32")
|
||||
|
||||
;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
|
||||
(define_insn_reservation "i6400_int_load" 3
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "move_type" "load"))
|
||||
(eq_attr "type" "load"))
|
||||
"i6400_agen_lsu")
|
||||
|
||||
;; store
|
||||
(define_insn_reservation "i6400_int_store" 1
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "move_type" "store"))
|
||||
(eq_attr "type" "store"))
|
||||
"i6400_agen_lsu")
|
||||
|
||||
;; prefetch
|
||||
(define_insn_reservation "i6400_int_prefetch" 3
|
||||
(define_insn_reservation "i6400_int_prefetch" 0
|
||||
(and (eq_attr "cpu" "i6400")
|
||||
(eq_attr "type" "prefetch"))
|
||||
"i6400_agen_lsu")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user