expr.c (store_expr): When converting expression to promoted equivalent type...
* expr.c (store_expr): When converting expression to promoted equivalent type, allow using SUBREG_REG of TARGET as the target of the expansion of EXP. * loop.c (basic_induction_var, case SUBREG): Always look inside. * config/alpha/alpha.c (rtx_equiv_function_matters): Delete decl. (alpha_emit_set_const): Handle SImode when can't make new pseudos. (alpha_emit_set_const_1, alpha_sa_mask): Use no_new_pseudos. * config/alpha/alpha.md (addsi3, subsi3): Don't use if optimizing. From-SVN: r49972
This commit is contained in:
Richard Kenner
parent
3256b817fc
commit
b76b08ef94
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@ -48,9 +48,6 @@ Boston, MA 02111-1307, USA. */
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#include "target-def.h"
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#include "debug.h"
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/* External data. */
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extern int rtx_equal_function_value_matters;
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/* Specify which cpu to schedule for. */
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enum processor_type alpha_cpu;
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@ -2231,15 +2228,29 @@ alpha_emit_set_const (target, mode, c, n)
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HOST_WIDE_INT c;
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int n;
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{
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rtx pat;
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rtx result = 0;
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rtx orig_target = target;
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int i;
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/* Try 1 insn, then 2, then up to N. */
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for (i = 1; i <= n; i++)
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if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
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return pat;
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/* If we can't make any pseudos, TARGET is an SImode hard register, we
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can't load this constant in one insn, do this in DImode. */
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if (no_new_pseudos && mode == SImode
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&& GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
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&& (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
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{
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target = gen_lowpart (DImode, target);
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mode = DImode;
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}
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return 0;
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/* Try 1 insn, then 2, then up to N. */
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for (i = 1; i <= n && result == 0; i++)
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result = alpha_emit_set_const_1 (target, mode, c, i);
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/* Allow for the case where we changed the mode of TARGET. */
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if (result == target)
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result = orig_target;
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return result;
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}
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/* Internal routine for the above to check for N or below insns. */
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@ -2255,8 +2266,7 @@ alpha_emit_set_const_1 (target, mode, c, n)
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int i, bits;
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/* Use a pseudo if highly optimizing and still generating RTL. */
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rtx subtarget
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= (flag_expensive_optimizations && rtx_equal_function_value_matters
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? 0 : target);
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= (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
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rtx temp;
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#if HOST_BITS_PER_WIDE_INT == 64
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@ -2321,8 +2331,7 @@ alpha_emit_set_const_1 (target, mode, c, n)
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we can't make pseudos, we can't do anything since the expand_binop
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and expand_unop calls will widen and try to make pseudos. */
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if (n == 1
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|| (mode == SImode && ! rtx_equal_function_value_matters))
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if (n == 1 || (mode == SImode && no_new_pseudos))
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return 0;
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/* Next, see if we can load a related constant and then shift and possibly
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@ -5857,7 +5866,7 @@ alpha_sa_mask (imaskP, fmaskP)
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the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
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we don't have valid register life info, but assemble_start_function
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wants to output .frame and .mask directives. */
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if (current_function_is_thunk && rtx_equal_function_value_matters)
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if (current_function_is_thunk && !no_new_pseudos)
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{
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*imaskP = 0;
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*fmaskP = 0;
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@ -518,31 +518,14 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
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(sign_extend:DI (match_dup 1)))]
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"")
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;; Do addsi3 the way expand_binop would do if we didn't have one. This
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;; generates better code. We have the anonymous addsi3 pattern below in
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;; case combine wants to make it.
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;; Don't say we have addsi3 if optimizing. This generates better code. We
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;; have the anonymous addsi3 pattern below in case combine wants to make it.
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
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(match_operand:SI 2 "add_operand" "")))]
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""
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{
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if (optimize)
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{
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rtx op1 = gen_lowpart (DImode, operands[1]);
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rtx op2 = gen_lowpart (DImode, operands[2]);
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if (! cse_not_expected)
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{
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_adddi3 (tmp, op1, op2));
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emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
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}
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else
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emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
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DONE;
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}
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})
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"! optimize"
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"")
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(define_insn "*addsi_internal"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
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@ -844,24 +827,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
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[(set (match_operand:SI 0 "register_operand" "")
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(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
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(match_operand:SI 2 "reg_or_8bit_operand" "")))]
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""
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{
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if (optimize)
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{
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rtx op1 = gen_lowpart (DImode, operands[1]);
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rtx op2 = gen_lowpart (DImode, operands[2]);
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if (! cse_not_expected)
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{
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rtx tmp = gen_reg_rtx (DImode);
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emit_insn (gen_subdi3 (tmp, op1, op2));
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emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
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}
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else
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emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
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DONE;
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}
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})
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"! optimize"
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"")
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(define_insn "*subsi_internal"
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[(set (match_operand:SI 0 "register_operand" "=r")
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@ -3989,6 +3989,8 @@ store_expr (exp, target, want_value)
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and then convert to the wider mode. Our value is the computed
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expression. */
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{
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rtx inner_target = 0;
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/* If we don't want a value, we can do the conversion inside EXP,
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which will often result in some optimizations. Do the conversion
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in two steps: first change the signedness, if needed, then
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@ -4009,9 +4011,11 @@ store_expr (exp, target, want_value)
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exp = convert (type_for_mode (GET_MODE (SUBREG_REG (target)),
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SUBREG_PROMOTED_UNSIGNED_P (target)),
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exp);
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inner_target = SUBREG_REG (target);
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}
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temp = expand_expr (exp, NULL_RTX, VOIDmode, 0);
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temp = expand_expr (exp, inner_target, VOIDmode, 0);
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/* If TEMP is a volatile MEM and we want a result value, make
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the access now so it gets done only once. Likewise if
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14
gcc/loop.c
14
gcc/loop.c
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@ -6127,13 +6127,13 @@ basic_induction_var (loop, x, mode, dest_reg, p, inc_val, mult_val, location)
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return 1;
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case SUBREG:
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/* If this is a SUBREG for a promoted variable, check the inner
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value. */
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if (SUBREG_PROMOTED_VAR_P (x))
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return basic_induction_var (loop, SUBREG_REG (x),
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GET_MODE (SUBREG_REG (x)),
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dest_reg, p, inc_val, mult_val, location);
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return 0;
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/* If what's inside the SUBREG is a BIV, then the SUBREG. This will
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handle addition of promoted variables.
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??? The comment at the start of this function is wrong: promoted
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variable increments don't look like it says they do. */
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return basic_induction_var (loop, SUBREG_REG (x),
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GET_MODE (SUBREG_REG (x)),
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dest_reg, p, inc_val, mult_val, location);
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case REG:
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/* If this register is assigned in a previous insn, look at its
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