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RISC-V: Improve caller-save code generation.

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Avoid paradoxical subregs when caller save.  This reduces stack frame size
due to smaller loads and stores, and more frequent rematerialization.

	PR target/93532
	* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
This commit is contained in:
Jim Wilson 2020-02-08 13:57:36 -08:00
parent aaa26bf496
commit b780f68e02
2 changed files with 12 additions and 0 deletions
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gcc/ChangeLog
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@ -1,3 +1,8 @@
2020-02-08 Jim Wilson <jimw@sifive.com>
PR target/93532
* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
Jakub Jelinek <jakub@redhat.com>

7
gcc/config/riscv/riscv.h
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@ -268,6 +268,13 @@ along with GCC; see the file COPYING3. If not see
1, 1 \
}
/* Select a register mode required for caller save of hard regno REGNO.
Contrary to what is documented, the default is not the smallest suitable
mode but the largest suitable mode for the given (REGNO, NREGS) pair and
it quickly creates paradoxical subregs that can be problematic. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
/* Internal macros to classify an ISA register's type. */
#define GP_REG_FIRST 0