rs6000-c.c (altivec_overloaded_builtins): Add __builtin_vec_revb builtins.
[gcc] 2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add __builtin_vec_revb builtins. * config/rs6000/rs6000-builtins.def (P9V_BUILTIN_XXBRQ_V16QI): Add built-in functions to support generation of the ISA 3.0 XXBR<x> vector byte reverse instructions. (P9V_BUILTIN_XXBRQ_V1TI): Likewise. (P9V_BUILTIN_XXBRD_V2DI): Likewise. (P9V_BUILTIN_XXBRD_V2DF): Likewise. (P9V_BUILTIN_XXBGW_V4SI): Likewise. (P9V_BUILTIN_XXBGW_V4SF): Likewise. (P9V_BUILTIN_XXBGH_V8HI): Likewise. (P9V_BUILTIN_VEC_REVB): Likewise. * config/rs6000/vsx.md (p9_xxbrq_v1ti): New insns/expanders to generate the ISA 3.0 XXBR<x> vector byte reverse instructions. (p9_xxbrq_v16qi): Likewise. (p9_xxbrd_<mode>, VSX_D iterator): Likewise. (p9_xxbrw_<mode>, VSX_W iterator): Likewise. (p9_xxbrh_v8hi): Likewise. * config/rs6000/altivec.h (vec_revb): Define if ISA 3.0. * doc/extend.texi (RS/6000 Altivec Built-ins): Document the vec_revb built-in functions. [gcc/testsuite] 2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-xxbr-1.c: New test. * gcc.target/powerpc/p9-xxbr-2.c: Likewise. From-SVN: r244593
This commit is contained in:
Michael Meissner
Michael Meissner
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c484627cf6
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b7d3a6a6b2
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@ -1,3 +1,27 @@
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2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
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__builtin_vec_revb builtins.
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* config/rs6000/rs6000-builtins.def (P9V_BUILTIN_XXBRQ_V16QI): Add
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built-in functions to support generation of the ISA 3.0 XXBR<x>
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vector byte reverse instructions.
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(P9V_BUILTIN_XXBRQ_V1TI): Likewise.
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(P9V_BUILTIN_XXBRD_V2DI): Likewise.
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(P9V_BUILTIN_XXBRD_V2DF): Likewise.
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(P9V_BUILTIN_XXBGW_V4SI): Likewise.
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(P9V_BUILTIN_XXBGW_V4SF): Likewise.
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(P9V_BUILTIN_XXBGH_V8HI): Likewise.
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(P9V_BUILTIN_VEC_REVB): Likewise.
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* config/rs6000/vsx.md (p9_xxbrq_v1ti): New insns/expanders to
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generate the ISA 3.0 XXBR<x> vector byte reverse instructions.
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(p9_xxbrq_v16qi): Likewise.
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(p9_xxbrd_<mode>, VSX_D iterator): Likewise.
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(p9_xxbrw_<mode>, VSX_W iterator): Likewise.
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(p9_xxbrh_v8hi): Likewise.
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* config/rs6000/altivec.h (vec_revb): Define if ISA 3.0.
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* doc/extend.texi (RS/6000 Altivec Built-ins): Document the
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vec_revb built-in functions.
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2017-01-18 Uros Bizjak <ubizjak@gmail.com>
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PR rtl-optimization/78952
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@ -444,6 +444,8 @@
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#define vec_xlx __builtin_vec_vextulx
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#define vec_xrx __builtin_vec_vexturx
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#define vec_revb __builtin_vec_revb
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#endif
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/* Predicates.
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@ -1954,6 +1954,14 @@ BU_P9V_64BIT_VSX_1 (VSESDP, "scalar_extract_sig", CONST, xsxsigdp)
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BU_P9V_VSX_1 (VSTDCNDP, "scalar_test_neg_dp", CONST, xststdcnegdp)
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BU_P9V_VSX_1 (VSTDCNSP, "scalar_test_neg_sp", CONST, xststdcnegsp)
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BU_P9V_VSX_1 (XXBRQ_V16QI, "xxbrq_v16qi", CONST, p9_xxbrq_v16qi)
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BU_P9V_VSX_1 (XXBRQ_V1TI, "xxbrq_v1ti", CONST, p9_xxbrq_v1ti)
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BU_P9V_VSX_1 (XXBRD_V2DI, "xxbrd_v2di", CONST, p9_xxbrd_v2di)
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BU_P9V_VSX_1 (XXBRD_V2DF, "xxbrd_v2df", CONST, p9_xxbrd_v2df)
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BU_P9V_VSX_1 (XXBRW_V4SI, "xxbrw_v4si", CONST, p9_xxbrw_v4si)
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BU_P9V_VSX_1 (XXBRW_V4SF, "xxbrw_v4sf", CONST, p9_xxbrw_v4sf)
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BU_P9V_VSX_1 (XXBRH_V8HI, "xxbrh_v8hi", CONST, p9_xxbrh_v8hi)
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/* 2 argument vsx scalar functions added in ISA 3.0 (power9). */
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BU_P9V_64BIT_VSX_2 (VSIEDP, "scalar_insert_exp", CONST, xsiexpdp)
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@ -1973,6 +1981,8 @@ BU_P9V_OVERLOAD_1 (VSTDCN, "scalar_test_neg")
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BU_P9V_OVERLOAD_1 (VSTDCNDP, "scalar_test_neg_dp")
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BU_P9V_OVERLOAD_1 (VSTDCNSP, "scalar_test_neg_sp")
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BU_P9V_OVERLOAD_1 (REVB, "revb")
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/* ISA 3.0 vector scalar overloaded 2 argument functions. */
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BU_P9V_OVERLOAD_2 (VSIEDP, "scalar_insert_exp")
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@ -5050,6 +5050,31 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
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RS6000_BTI_unsigned_V16QI, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
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RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
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{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
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RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
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/* Crypto builtins. */
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{ CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
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@ -3899,6 +3899,51 @@
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[(set_attr "type" "vecperm")])
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;; Support for ISA 3.0 vector byte reverse
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;; Swap all bytes with in a vector
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(define_insn "p9_xxbrq_v1ti"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=wa")
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(bswap:V1TI (match_operand:V1TI 1 "vsx_register_operand" "wa")))]
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"TARGET_P9_VECTOR"
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"xxbrq %x0,%x1"
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[(set_attr "type" "vecperm")])
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(define_expand "p9_xxbrq_v16qi"
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[(use (match_operand:V16QI 0 "vsx_register_operand" "=wa"))
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(use (match_operand:V16QI 1 "vsx_register_operand" "=wa"))]
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"TARGET_P9_VECTOR"
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{
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rtx op0 = gen_lowpart (V1TImode, operands[0]);
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rtx op1 = gen_lowpart (V1TImode, operands[1]);
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emit_insn (gen_p9_xxbrq_v1ti (op0, op1));
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DONE;
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})
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;; Swap all bytes in each 64-bit element
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(define_insn "p9_xxbrd_<mode>"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
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(bswap:VSX_D (match_operand:VSX_D 1 "vsx_register_operand" "wa")))]
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"TARGET_P9_VECTOR"
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"xxbrd %x0,%x1"
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[(set_attr "type" "vecperm")])
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;; Swap all bytes in each 32-bit element
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(define_insn "p9_xxbrw_<mode>"
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[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
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(bswap:VSX_W (match_operand:VSX_W 1 "vsx_register_operand" "wa")))]
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"TARGET_P9_VECTOR"
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"xxbrw %x0,%x1"
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[(set_attr "type" "vecperm")])
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;; Swap all bytes in each 16-bit element
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(define_insn "p9_xxbrh_v8hi"
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[(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
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(bswap:V8HI (match_operand:V8HI 1 "vsx_register_operand" "wa")))]
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"TARGET_P9_VECTOR"
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"xxbrh %x0,%x1"
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[(set_attr "type" "vecperm")])
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;; Operand numbers for the following peephole2
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(define_constants
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@ -18231,6 +18231,34 @@ second argument vector contains the mask beginning in bits 11:15,
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the mask end in bits 19:23, and the shift count in bits 27:31,
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of each element.
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If the ISA 3.0 instruction set additions (@option{-mcpu=power9})
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are available:
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@smallexample
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vector signed char vec_revb (vector signed char);
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vector unsigned char vec_revb (vector unsigned char);
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vector short vec_revb (vector short);
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vector unsigned short vec_revb (vector unsigned short);
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vector int vec_revb (vector int);
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vector unsigned int vec_revb (vector unsigned int);
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vector float vec_revb (vector float);
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vector long long vec_revb (vector long long);
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vector unsigned long long vec_revb (vector unsigned long long);
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vector double vec_revb (vector double);
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@end smallexample
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On 64-bit targets, if the ISA 3.0 additions (@option{-mcpu=power9})
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are available:
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@smallexample
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vector long vec_revb (vector long);
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vector unsigned long vec_revb (vector unsigned long);
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vector __int128_t vec_revb (vector __int128_t);
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vector __uint128_t vec_revb (vector __uint128_t);
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@end smallexample
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The @code{vec_revb} built-in function reverses the bytes on an element
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by element basis. A vector of @code{vector unsigned char} or
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@code{vector signed char} reverses the bytes in the whole word.
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If the cryptographic instructions are enabled (@option{-mcrypto} or
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@option{-mcpu=power8}), the following builtins are enabled.
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@ -1,3 +1,8 @@
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2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com>
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* gcc.target/powerpc/p9-xxbr-1.c: New test.
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* gcc.target/powerpc/p9-xxbr-2.c: Likewise.
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2017-01-18 Nathan Sidwell <nathan@acm.org>
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PR c++/78488
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@ -0,0 +1,67 @@
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/* { dg-do compile { target { powerpc64le-*-* } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O3" } */
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#include <altivec.h>
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/* Verify P9 vec_revb builtin generates the XXBR{Q,D,W,H} instructions. */
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vector char
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rev_char (vector char a)
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{
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return vec_revb (a); /* XXBRQ. */
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}
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vector signed char
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rev_schar (vector signed char a)
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{
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return vec_revb (a); /* XXBRQ. */
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}
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vector unsigned char
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rev_uchar (vector unsigned char a)
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{
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return vec_revb (a); /* XXBRQ. */
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}
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vector short
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rev_short (vector short a)
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{
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return vec_revb (a); /* XXBRH. */
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}
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vector unsigned short
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rev_ushort (vector unsigned short a)
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{
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return vec_revb (a); /* XXBRH. */
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}
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vector int
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rev_int (vector int a)
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{
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return vec_revb (a); /* XXBRW. */
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}
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vector unsigned int
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rev_uint (vector unsigned int a)
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{
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return vec_revb (a); /* XXBRW. */
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}
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vector float
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rev_float (vector float a)
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{
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return vec_revb (a); /* XXBRW. */
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}
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vector double
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rev_double (vector double a)
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{
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return vec_revb (a); /* XXBRD. */
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}
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/* { dg-final { scan-assembler-count "xxbrd" 1 } } */
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/* { dg-final { scan-assembler-count "xxbrh" 2 } } */
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/* { dg-final { scan-assembler-count "xxbrq" 3 } } */
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/* { dg-final { scan-assembler-count "xxbrw" 3 } } */
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@ -0,0 +1,36 @@
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/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O3" } */
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#include <altivec.h>
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/* Verify P9 vec_revb builtin generates the XXBR{Q,D,W,H} instructions. This
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test only tests the vector types that need a 64-bit environment. */
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vector long
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rev_long (vector long a)
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{
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return vec_revb (a); /* XXBRD. */
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}
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vector unsigned long
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rev_ulong (vector unsigned long a)
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{
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return vec_revb (a); /* XXBRD. */
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}
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vector __int128_t
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rev_int128 (vector __int128_t a)
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{
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return vec_revb (a); /* XXBRQ. */
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}
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vector __uint128_t
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rev_uint128 (vector __uint128_t a)
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{
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return vec_revb (a); /* XXBRQ. */
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}
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/* { dg-final { scan-assembler-count "xxbrd" 2 } } */
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/* { dg-final { scan-assembler-count "xxbrq" 2 } } */
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