aarch64-simd-builtins.def: Separate sq<r>dmulh_lane entries into lane and laneq entries.
2013-01-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
entries into lane and laneq entries.
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
AdvSIMD scalar modes.
(aarch64_sq<r>dmulh_laneq<mode>): New.
(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
modes.
* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
builtin implementations to relfect changes in RTL in aarch64-simd.md.
* config/aarch64/iterators.md (VCOND): New.
(VCONQ): New.
From-SVN: r195467
This commit is contained in:
Tejas Belagod
Tejas Belagod
parent
556f9906c5
commit
b7d7d917bd
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@ -1,3 +1,17 @@
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2013-01-25 Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
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entries into lane and laneq entries.
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* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
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AdvSIMD scalar modes.
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(aarch64_sq<r>dmulh_laneq<mode>): New.
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(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
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modes.
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* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
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builtin implementations to relfect changes in RTL in aarch64-simd.md.
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* config/aarch64/iterators.md (VCOND): New.
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(VCONQ): New.
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2013-01-25 Georg-Johann Lay <avr@gjlay.de>
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PR target/54222
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@ -142,9 +142,13 @@
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/* Implemented by aarch64_sq<r>dmulh<mode>. */
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BUILTIN_VSDQ_HSI (BINOP, sqdmulh)
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BUILTIN_VSDQ_HSI (BINOP, sqrdmulh)
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/* Implemented by aarch64_sq<r>dmulh_lane<mode>. */
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BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_lane)
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BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_lane)
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/* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */
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BUILTIN_VDQHS (TERNOP, sqdmulh_lane)
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BUILTIN_VDQHS (TERNOP, sqdmulh_laneq)
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BUILTIN_VDQHS (TERNOP, sqrdmulh_lane)
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BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq)
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BUILTIN_SD_HSI (TERNOP, sqdmulh_lane)
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BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane)
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BUILTIN_VSDQ_I_DI (BINOP, sshl_n)
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BUILTIN_VSDQ_I_DI (BINOP, ushl_n)
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@ -2210,17 +2210,49 @@
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;; sq<r>dmulh_lane
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(define_insn "aarch64_sq<r>dmulh_lane<mode>"
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[(set (match_operand:VSDQ_HSI 0 "register_operand" "=w")
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(unspec:VSDQ_HSI
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[(match_operand:VSDQ_HSI 1 "register_operand" "w")
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(unspec:VDQHS
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[(match_operand:VDQHS 1 "register_operand" "w")
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(vec_select:<VEL>
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(match_operand:<VCON> 2 "register_operand" "<vwx>")
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(match_operand:<VCOND> 2 "register_operand" "<vwx>")
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(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
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VQDMULH))]
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCON>mode));
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return \"sq<r>dmulh\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]\";"
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
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return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
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[(set_attr "simd_type" "simd_sat_mul")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_sq<r>dmulh_laneq<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(unspec:VDQHS
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[(match_operand:VDQHS 1 "register_operand" "w")
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(vec_select:<VEL>
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(match_operand:<VCONQ> 2 "register_operand" "<vwx>")
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(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
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VQDMULH))]
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
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return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
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[(set_attr "simd_type" "simd_sat_mul")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_sq<r>dmulh_lane<mode>"
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[(set (match_operand:SD_HSI 0 "register_operand" "=w")
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(unspec:SD_HSI
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[(match_operand:SD_HSI 1 "register_operand" "w")
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(vec_select:<VEL>
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(match_operand:<VCONQ> 2 "register_operand" "<vwx>")
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(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
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VQDMULH))]
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
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return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
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[(set_attr "simd_type" "simd_sat_mul")
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(set_attr "simd_mode" "<MODE>")]
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)
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@ -18877,49 +18877,49 @@ vpaddd_s64 (int64x2_t __a)
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
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{
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return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
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return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c);
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
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{
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return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
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return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c);
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
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{
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return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
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return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c);
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
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{
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return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
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return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c);
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}
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
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{
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return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
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return __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c);
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
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{
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return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
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return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c);
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
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{
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return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
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return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c);
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
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{
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return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
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return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c);
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}
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/* Table intrinsics. */
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@ -21974,29 +21974,25 @@ vqdmlsls_lane_s32 (int64x1_t __a, int32x1_t __b, int32x4_t __c, const int __d)
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
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{
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int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0)));
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return __builtin_aarch64_sqdmulh_lanev4hi (__a, __tmp, __c);
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return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
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{
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int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0)));
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return __builtin_aarch64_sqdmulh_lanev2si (__a, __tmp, __c);
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return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
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{
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int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0)));
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return __builtin_aarch64_sqdmulh_lanev8hi (__a, __tmp, __c);
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return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
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{
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int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0)));
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return __builtin_aarch64_sqdmulh_lanev4si (__a, __tmp, __c);
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return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
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}
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__extension__ static __inline int16x1_t __attribute__ ((__always_inline__))
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@ -22290,29 +22286,25 @@ vqnegs_s32 (int32x1_t __a)
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
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{
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int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0)));
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return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __tmp, __c);
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return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
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{
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int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0)));
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return __builtin_aarch64_sqrdmulh_lanev2si (__a, __tmp, __c);
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return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
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{
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int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0)));
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return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __tmp, __c);
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return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
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{
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int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0)));
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return __builtin_aarch64_sqrdmulh_lanev4si (__a, __tmp, __c);
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return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
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}
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__extension__ static __inline int16x1_t __attribute__ ((__always_inline__))
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@ -339,6 +339,22 @@
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(SI "SI") (HI "HI")
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(QI "QI")])
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;; Define container mode for lane selection.
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(define_mode_attr VCOND [(V4HI "V4HI") (V8HI "V4HI")
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(V2SI "V2SI") (V4SI "V2SI")
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(DI "DI") (V2DI "DI")
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(V2SF "V2SF") (V4SF "V2SF")
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(V2DF "DF")])
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;; Define container mode for lane selection.
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(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
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(V4HI "V8HI") (V8HI "V8HI")
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(V2SI "V4SI") (V4SI "V4SI")
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(DI "V2DI") (V2DI "V2DI")
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(V2SF "V2SF") (V4SF "V4SF")
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(V2DF "V2DF") (SI "V4SI")
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(HI "V8HI") (QI "V16QI")])
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;; Define container mode for lane selection.
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(define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI")
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(V4HI "V8HI") (V8HI "V8HI")
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