From b81f53a13c2f0f6df57f82b2478e6398e9cf0f3a Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Tue, 23 May 2000 10:42:56 +0000 Subject: [PATCH] alpha.c: Remove #ifdef HAIFA since now only scheduler. * config/alpha/alpha.c: Remove #ifdef HAIFA since now only scheduler. (alpha_start_function): Never write ..ng label if VMS or NT. (alpha_align_insns): Remove GP_IN_USE arg. Alignment now unsigned. (alpha_reorg): Don't pass GP_IN_USE arg to alpha_align_insns. * config/alpha/alpha.md (prologue_ldgp): Split into one define_expand and two define_insn's. From-SVN: r34104 --- gcc/ChangeLog | 10 +++++++ gcc/config/alpha/alpha.c | 59 +++++++++++++++------------------------ gcc/config/alpha/alpha.md | 33 +++++++++++++++++++--- 3 files changed, 62 insertions(+), 40 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1822b71f55a..68ee38034fa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Tue May 23 06:50:29 2000 Richard Kenner + + * config/alpha/alpha.c: Remove #ifdef HAIFA since now only scheduler. + (alpha_start_function): Never write ..ng label if VMS or NT. + (alpha_align_insns): Remove GP_IN_USE arg. + Alignment now unsigned. + (alpha_reorg): Don't pass GP_IN_USE arg to alpha_align_insns. + * config/alpha/alpha.md (prologue_ldgp): Split into one define_expand + and two define_insn's. + 2000-05-22 Richard Henderson * combine.c (simplify_comparison): Use trunc_int_for_mode. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 483ae69274c..d19f0b0cdf0 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -4434,7 +4434,8 @@ alpha_start_function (file, fnname, decl) /* If the function needs GP, we'll write the "..ng" label there. Otherwise, do it here. */ - if (! alpha_function_needs_gp) + if (! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT + && ! alpha_function_needs_gp) { putc ('$', file); assemble_name (file, fnname); @@ -5179,7 +5180,6 @@ alpha_handle_trap_shadows (insns) } } -#ifdef HAIFA /* Alpha can only issue instruction groups simultaneously if they are suitibly aligned. This is very processor-specific. */ @@ -5203,13 +5203,13 @@ enum alphaev5_pipe { static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx)); static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx)); -static rtx alphaev4_next_group PARAMS ((rtx, int*, int*)); -static rtx alphaev5_next_group PARAMS ((rtx, int*, int*)); -static rtx alphaev4_next_nop PARAMS ((int*)); -static rtx alphaev5_next_nop PARAMS ((int*)); +static rtx alphaev4_next_group PARAMS ((rtx, int *, int *)); +static rtx alphaev5_next_group PARAMS ((rtx, int *, int *)); +static rtx alphaev4_next_nop PARAMS ((int *)); +static rtx alphaev5_next_nop PARAMS ((int *)); static void alpha_align_insns - PARAMS ((rtx, int, rtx (*)(rtx, int*, int*), rtx (*)(int*), int)); + PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *))); static enum alphaev4_pipe alphaev4_insn_pipe (insn) @@ -5249,7 +5249,7 @@ alphaev4_insn_pipe (insn) return EV4_IB1; default: - abort(); + abort (); } } @@ -5596,15 +5596,14 @@ alphaev5_next_nop (pin_use) /* The instruction group alignment main loop. */ static void -alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use) +alpha_align_insns (insns, max_align, next_group, next_nop) rtx insns; - int max_align; - rtx (*next_group) PARAMS ((rtx, int*, int*)); - rtx (*next_nop) PARAMS ((int*)); - int gp_in_use; + unsigned int max_align; + rtx (*next_group) PARAMS ((rtx, int *, int *)); + rtx (*next_nop) PARAMS ((int *)); { /* ALIGN is the known alignment for the insn group. */ - int align; + unsigned int align; /* OFS is the offset of the current insn in the insn group. */ int ofs; int prev_in_use, in_use, len; @@ -5613,35 +5612,29 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use) /* Let shorten branches care for assigning alignments to code labels. */ shorten_branches (insns); - align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < max_align - ? FUNCTION_BOUNDARY/BITS_PER_UNIT : max_align); + align = (FUNCTION_BOUNDARY / BITS_PER_UNIT < max_align + ? FUNCTION_BOUNDARY / BITS_PER_UNIT : max_align); - /* Account for the initial GP load, which happens before the scheduled - prologue we emitted as RTL. */ ofs = prev_in_use = 0; - if (alpha_does_function_need_gp()) - { - ofs = 8 & (align - 1); - prev_in_use = gp_in_use; - } - i = insns; if (GET_CODE (i) == NOTE) i = next_nonnote_insn (i); while (i) { - next = (*next_group)(i, &in_use, &len); + next = (*next_group) (i, &in_use, &len); /* When we see a label, resync alignment etc. */ if (GET_CODE (i) == CODE_LABEL) { - int new_align = 1 << label_to_alignment (i); + unsigned int new_align = 1 << label_to_alignment (i); + if (new_align >= align) { align = new_align < max_align ? new_align : max_align; ofs = 0; } + else if (ofs & (new_align-1)) ofs = (ofs | (new_align-1)) + 1; if (len != 0) @@ -5666,7 +5659,7 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use) realign the output. */ else if (align < len) { - int new_log_align = len > 8 ? 4 : 3; + unsigned int new_log_align = len > 8 ? 4 : 3; rtx where; where = prev_nonnote_insn (i); @@ -5717,7 +5710,6 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use) i = next; } } -#endif /* HAIFA */ /* Machine dependant reorg pass. */ @@ -5728,24 +5720,19 @@ alpha_reorg (insns) if (alpha_tp != ALPHA_TP_PROG || flag_exceptions) alpha_handle_trap_shadows (insns); -#ifdef HAIFA /* Due to the number of extra trapb insns, don't bother fixing up alignment when trap precision is instruction. Moreover, we can - only do our job when sched2 is run and Haifa is our scheduler. */ + only do our job when sched2 is run. */ if (optimize && !optimize_size && alpha_tp != ALPHA_TP_INSN && flag_schedule_insns_after_reload) { if (alpha_cpu == PROCESSOR_EV4) - alpha_align_insns (insns, 8, alphaev4_next_group, - alphaev4_next_nop, EV4_IB0); + alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop); else if (alpha_cpu == PROCESSOR_EV5) - alpha_align_insns (insns, 16, alphaev5_next_group, - alphaev5_next_nop, EV5_E01 | EV5_E0); + alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop); } -#endif } - /* Check a floating-point value for validity for a particular machine mode. */ diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 835ffee14f2..10b5aa1b50b 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -5493,11 +5493,29 @@ DONE; }") -(define_insn "prologue_ldgp" - [(unspec_volatile [(const_int 0)] 9)] +;; These take care of emitting the ldgp insn in the prologue. This will be +;; an lda/ldah pair and we want to align them properly. So we have two +;; unspec_volatile insns, the first of which emits the ldgp assembler macro +;; and the second of which emits nothing. However, both are marked as type +;; IADD (the default) so the alignment code in alpha.c does the right thing +;; with them. + +(define_expand "prologue_ldgp" + [(unspec_volatile [(const_int 0)] 9) + (unspec_volatile [(const_int 0)] 10)] "" + "") + +(define_insn "*prologue_ldgp_1" + [(unspec_volatile [(const_int 0)] 9)] + "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT" "ldgp $29,0($27)\\n$%~..ng:") +(define_insn "*prologue_ldgp_2" + [(unspec_volatile [(const_int 0)] 10)] + "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT" + "") + (define_insn "init_fp" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "register_operand" "r")) @@ -5508,12 +5526,19 @@ (define_expand "epilogue" [(return)] "" - "alpha_expand_epilogue ();") + " +{ + alpha_expand_epilogue (); +}") (define_expand "sibcall_epilogue" [(return)] "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT" - "alpha_expand_epilogue (); DONE;") + " +{ + alpha_expand_epilogue (); + DONE; +}") (define_expand "eh_epilogue" [(use (match_operand:DI 0 "register_operand" "r"))