alpha.c: Remove #ifdef HAIFA since now only scheduler.
* config/alpha/alpha.c: Remove #ifdef HAIFA since now only scheduler. (alpha_start_function): Never write ..ng label if VMS or NT. (alpha_align_insns): Remove GP_IN_USE arg. Alignment now unsigned. (alpha_reorg): Don't pass GP_IN_USE arg to alpha_align_insns. * config/alpha/alpha.md (prologue_ldgp): Split into one define_expand and two define_insn's. From-SVN: r34104
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@ -1,3 +1,13 @@
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Tue May 23 06:50:29 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
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* config/alpha/alpha.c: Remove #ifdef HAIFA since now only scheduler.
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(alpha_start_function): Never write ..ng label if VMS or NT.
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(alpha_align_insns): Remove GP_IN_USE arg.
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Alignment now unsigned.
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(alpha_reorg): Don't pass GP_IN_USE arg to alpha_align_insns.
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* config/alpha/alpha.md (prologue_ldgp): Split into one define_expand
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and two define_insn's.
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2000-05-22 Richard Henderson <rth@cygnus.com>
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* combine.c (simplify_comparison): Use trunc_int_for_mode.
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@ -4434,7 +4434,8 @@ alpha_start_function (file, fnname, decl)
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/* If the function needs GP, we'll write the "..ng" label there.
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Otherwise, do it here. */
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if (! alpha_function_needs_gp)
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if (! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT
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&& ! alpha_function_needs_gp)
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{
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putc ('$', file);
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assemble_name (file, fnname);
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@ -5179,7 +5180,6 @@ alpha_handle_trap_shadows (insns)
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}
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}
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#ifdef HAIFA
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/* Alpha can only issue instruction groups simultaneously if they are
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suitibly aligned. This is very processor-specific. */
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@ -5209,7 +5209,7 @@ static rtx alphaev4_next_nop PARAMS ((int*));
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static rtx alphaev5_next_nop PARAMS ((int *));
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static void alpha_align_insns
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PARAMS ((rtx, int, rtx (*)(rtx, int*, int*), rtx (*)(int*), int));
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PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *)));
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static enum alphaev4_pipe
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alphaev4_insn_pipe (insn)
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@ -5596,15 +5596,14 @@ alphaev5_next_nop (pin_use)
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/* The instruction group alignment main loop. */
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static void
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alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
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alpha_align_insns (insns, max_align, next_group, next_nop)
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rtx insns;
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int max_align;
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unsigned int max_align;
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rtx (*next_group) PARAMS ((rtx, int *, int *));
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rtx (*next_nop) PARAMS ((int *));
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int gp_in_use;
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{
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/* ALIGN is the known alignment for the insn group. */
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int align;
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unsigned int align;
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/* OFS is the offset of the current insn in the insn group. */
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int ofs;
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int prev_in_use, in_use, len;
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@ -5616,15 +5615,7 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
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align = (FUNCTION_BOUNDARY / BITS_PER_UNIT < max_align
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? FUNCTION_BOUNDARY / BITS_PER_UNIT : max_align);
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/* Account for the initial GP load, which happens before the scheduled
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prologue we emitted as RTL. */
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ofs = prev_in_use = 0;
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if (alpha_does_function_need_gp())
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{
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ofs = 8 & (align - 1);
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prev_in_use = gp_in_use;
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}
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i = insns;
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if (GET_CODE (i) == NOTE)
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i = next_nonnote_insn (i);
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@ -5636,12 +5627,14 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
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/* When we see a label, resync alignment etc. */
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if (GET_CODE (i) == CODE_LABEL)
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{
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int new_align = 1 << label_to_alignment (i);
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unsigned int new_align = 1 << label_to_alignment (i);
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if (new_align >= align)
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{
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align = new_align < max_align ? new_align : max_align;
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ofs = 0;
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}
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else if (ofs & (new_align-1))
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ofs = (ofs | (new_align-1)) + 1;
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if (len != 0)
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@ -5666,7 +5659,7 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
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realign the output. */
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else if (align < len)
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{
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int new_log_align = len > 8 ? 4 : 3;
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unsigned int new_log_align = len > 8 ? 4 : 3;
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rtx where;
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where = prev_nonnote_insn (i);
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@ -5717,7 +5710,6 @@ alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
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i = next;
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}
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}
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#endif /* HAIFA */
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/* Machine dependant reorg pass. */
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@ -5728,24 +5720,19 @@ alpha_reorg (insns)
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if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
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alpha_handle_trap_shadows (insns);
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#ifdef HAIFA
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/* Due to the number of extra trapb insns, don't bother fixing up
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alignment when trap precision is instruction. Moreover, we can
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only do our job when sched2 is run and Haifa is our scheduler. */
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only do our job when sched2 is run. */
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if (optimize && !optimize_size
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&& alpha_tp != ALPHA_TP_INSN
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&& flag_schedule_insns_after_reload)
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{
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if (alpha_cpu == PROCESSOR_EV4)
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alpha_align_insns (insns, 8, alphaev4_next_group,
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alphaev4_next_nop, EV4_IB0);
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alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop);
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else if (alpha_cpu == PROCESSOR_EV5)
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alpha_align_insns (insns, 16, alphaev5_next_group,
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alphaev5_next_nop, EV5_E01 | EV5_E0);
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alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop);
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}
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#endif
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}
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/* Check a floating-point value for validity for a particular machine mode. */
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@ -5493,11 +5493,29 @@
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DONE;
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}")
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(define_insn "prologue_ldgp"
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[(unspec_volatile [(const_int 0)] 9)]
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;; These take care of emitting the ldgp insn in the prologue. This will be
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;; an lda/ldah pair and we want to align them properly. So we have two
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;; unspec_volatile insns, the first of which emits the ldgp assembler macro
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;; and the second of which emits nothing. However, both are marked as type
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;; IADD (the default) so the alignment code in alpha.c does the right thing
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;; with them.
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(define_expand "prologue_ldgp"
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[(unspec_volatile [(const_int 0)] 9)
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(unspec_volatile [(const_int 0)] 10)]
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""
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"")
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(define_insn "*prologue_ldgp_1"
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[(unspec_volatile [(const_int 0)] 9)]
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"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
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"ldgp $29,0($27)\\n$%~..ng:")
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(define_insn "*prologue_ldgp_2"
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[(unspec_volatile [(const_int 0)] 10)]
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"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
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"")
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(define_insn "init_fp"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "register_operand" "r"))
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(define_expand "epilogue"
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[(return)]
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""
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"alpha_expand_epilogue ();")
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"
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{
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alpha_expand_epilogue ();
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}")
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(define_expand "sibcall_epilogue"
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[(return)]
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"!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
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"alpha_expand_epilogue (); DONE;")
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"
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{
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alpha_expand_epilogue ();
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DONE;
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}")
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(define_expand "eh_epilogue"
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[(use (match_operand:DI 0 "register_operand" "r"))
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