v850.c (F): New function.
* config/v850/v850.c (F): New function. Mark the given insn as being frame related. (v850_all_frame_related): New function. Mark the given push insn as being frame related. (v850_pass_by_reference): When using the RH850 ABI do not pass arguments by reference. (v850_strict_argument_naming): Delete function. (v850_function_arg): Use word alignment with the RH850 ABI. (v850_arg_partial_bytes): Likewise. (v850_function_arg_advance): Likewise. (v850_print_operand): Handle CONST_INT and CONST_DOUBLE. (compute_register_save_size): Use df_regs_ever_live_p. (increment_stack): Mark prologue adjustments as being frame related. (expand_prologue): Handle pretend args. Mark insns generated as being frame related. (expand_epilogue): Likewise. (v850_return_in_memory): When using the RH850 ABI return aggregates in memory. (v850_setup_incoming_varargs): Delete function. (v850_option_override): New function. (TARGET_DEBUG_UNWIND_INFO): Delete definition. (TARGET_SETUP_INCOMING_VARARGS): Likewise. (TARGET_STRICT_ARGUMENT_NAMING): Likewise. (TARGET_OPTION_OVERRIDE): Define. * config/v850/v850.h (ASM_SPEC): Pass 8byte-align and gcc-abi options on to assembler. (LINK_SPEC): Likewise. (TARGET_CPU_CPP_BUILTINS): Define __V850_8BYTE_ALIGN__ and __V850_GCC_ABI__. (STACK_BOUNDARY): Set to BIGGEST_ALIGNMENT. (FUNCTION_BOUNDARY): With the RH850 ABI always 32-bit alignment. (BIGGEST_ALIGNMENT): With -8byte-align set to 64-bits. (BIGGEST_FIELD_ALIGNMENT): Likewise. (enum reg_class): Swap EVEN_REGS and GENERAL_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (struct cum_arg): Delete anonymous_args field. (INIT_CUMULATIVE_ARGS): Update. (PREFERRED_DEBUG): Set to DWARF2_DEBUG. (DWARF2_FRAME_INFO): Define. (DWARF2_UNWIND_INFO): Define. (INCOMING_RETURN_ADDR_RTX): Define. (DWARF_FRAME_RETURN_COLUMN): Define. (TARGET_USE_FPU): Define. * config/v850/v850.md: Replace TARGET_V850E2V3 in floating point insns with TARGET_USE_FPU. (fixuns_truncsfsi2): New pattern. (fixuns_truncdfsi2): New pattern. (fix_truncsfdi2): New pattern. (fixuns_truncsfdi2): New pattern. (fix_truncdfdi2): New pattern. (fixuns_truncdfdi2): New pattern. (unsfloatsisf2): New pattern. (unsfloatsidf2): New pattern. (floatdisf2): New pattern. (unsfloatdisf2): New pattern. (floatdidf2): New pattern. (unsfloatdidf2): New pattern. (fnmasf4): Fix RTl description. (fnmssf4): Likewise. * config/v850/v850.opt (mrelax): New option. (mlong-jumps): Likewise. (msoft-float): Likewise. (mhard-float): Likewise. (mrh850-abi): Likewise. (mgcc-abi): Likewise. (m8byte-align): Likewise. * config/v850/t-v850 (MULTILIB_OPTIONS): Update multilib options. (MULTILIB_DIRNAMES): Likewise. From-SVN: r193661
This commit is contained in:
Nick Clifton
Nick Clifton
parent
aef5ffaaab
commit
b84d824df4
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@ -2,6 +2,79 @@
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* config/i386/i386.c (ix86_expand_call): Emit CLOBBERs in VOIDmode.
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2012-11-20 Nick Clifton <nickc@redhat.com>
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* config/v850/v850.c (F): New function. Mark the given insn as
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being frame related.
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(v850_all_frame_related): New function. Mark the given push insn
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as being frame related.
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(v850_pass_by_reference): When using the RH850 ABI do not pass
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arguments by reference.
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(v850_strict_argument_naming): Delete function.
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(v850_function_arg): Use word alignment with the RH850 ABI.
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(v850_arg_partial_bytes): Likewise.
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(v850_function_arg_advance): Likewise.
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(v850_print_operand): Handle CONST_INT and CONST_DOUBLE.
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(compute_register_save_size): Use df_regs_ever_live_p.
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(increment_stack): Mark prologue adjustments as being frame
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related.
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(expand_prologue): Handle pretend args. Mark insns generated as
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being frame related.
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(expand_epilogue): Likewise.
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(v850_return_in_memory): When using the RH850 ABI return
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aggregates in memory.
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(v850_setup_incoming_varargs): Delete function.
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(v850_option_override): New function.
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(TARGET_DEBUG_UNWIND_INFO): Delete definition.
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(TARGET_SETUP_INCOMING_VARARGS): Likewise.
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(TARGET_STRICT_ARGUMENT_NAMING): Likewise.
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(TARGET_OPTION_OVERRIDE): Define.
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* config/v850/v850.h (ASM_SPEC): Pass 8byte-align and gcc-abi
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options on to assembler.
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(LINK_SPEC): Likewise.
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(TARGET_CPU_CPP_BUILTINS): Define __V850_8BYTE_ALIGN__ and
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__V850_GCC_ABI__.
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(STACK_BOUNDARY): Set to BIGGEST_ALIGNMENT.
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(FUNCTION_BOUNDARY): With the RH850 ABI always 32-bit alignment.
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(BIGGEST_ALIGNMENT): With -8byte-align set to 64-bits.
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(BIGGEST_FIELD_ALIGNMENT): Likewise.
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(enum reg_class): Swap EVEN_REGS and GENERAL_REGS.
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(REG_CLASS_NAMES): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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(struct cum_arg): Delete anonymous_args field.
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(INIT_CUMULATIVE_ARGS): Update.
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(PREFERRED_DEBUG): Set to DWARF2_DEBUG.
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(DWARF2_FRAME_INFO): Define.
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(DWARF2_UNWIND_INFO): Define.
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(INCOMING_RETURN_ADDR_RTX): Define.
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(DWARF_FRAME_RETURN_COLUMN): Define.
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(TARGET_USE_FPU): Define.
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* config/v850/v850.md: Replace TARGET_V850E2V3 in floating point
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insns with TARGET_USE_FPU.
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(fixuns_truncsfsi2): New pattern.
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(fixuns_truncdfsi2): New pattern.
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(fix_truncsfdi2): New pattern.
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(fixuns_truncsfdi2): New pattern.
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(fix_truncdfdi2): New pattern.
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(fixuns_truncdfdi2): New pattern.
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(unsfloatsisf2): New pattern.
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(unsfloatsidf2): New pattern.
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(floatdisf2): New pattern.
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(unsfloatdisf2): New pattern.
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(floatdidf2): New pattern.
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(unsfloatdidf2): New pattern.
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(fnmasf4): Fix RTl description.
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(fnmssf4): Likewise.
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* config/v850/v850.opt (mrelax): New option.
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(mlong-jumps): Likewise.
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(msoft-float): Likewise.
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(mhard-float): Likewise.
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(mrh850-abi): Likewise.
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(mgcc-abi): Likewise.
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(m8byte-align): Likewise.
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* config/v850/t-v850 (MULTILIB_OPTIONS): Update multilib options.
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(MULTILIB_DIRNAMES): Likewise.
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2012-11-20 Nick Clifton <nickc@redhat.com>
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* config/rx/rx.c (rx_function_arg_boundary): When using the RX ABI
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@ -1,5 +1,5 @@
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# Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2008, 2009, 2010,
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# 2011 Free Software Foundation, Inc.
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# 2011, 2012 Free Software Foundation, Inc.
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#
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# This file is part of GCC.
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#
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@ -18,9 +18,8 @@
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# <http://www.gnu.org/licenses/>.
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# Create target-specific versions of the libraries
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MULTILIB_OPTIONS = mv850/mv850e/mv850e2/mv850e2v3
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MULTILIB_DIRNAMES = v850 v850e v850e2 v850e2v3
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MULTILIB_MATCHES = mv850e=mv850e1
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MULTILIB_OPTIONS = m8byte-align mgcc-abi msoft-float
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MULTILIB_DIRNAMES = 8byte gcc-abi soft-float
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TCFLAGS = -mno-app-regs -msmall-sld -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
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@ -72,6 +72,35 @@ static GTY(()) section * tdata_section;
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static GTY(()) section * zdata_section;
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static GTY(()) section * zbss_section;
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/* We use this to wrap all emitted insns in the prologue. */
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static rtx
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F (rtx x)
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{
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if (GET_CODE (x) != CLOBBER)
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RTX_FRAME_RELATED_P (x) = 1;
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return x;
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}
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/* Mark all the subexpressions of the PARALLEL rtx PAR as
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frame-related. Return PAR.
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dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
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PARALLEL rtx other than the first if they do not have the
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FRAME_RELATED flag set on them. */
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static rtx
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v850_all_frame_related (rtx par)
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{
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int len = XVECLEN (par, 0);
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int i;
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gcc_assert (GET_CODE (par) == PARALLEL);
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for (i = 0; i < len; i++)
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F (XVECEXP (par, 0, i));
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return par;
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}
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/* Handle the TARGET_PASS_BY_REFERENCE target hook.
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Specify whether to pass the argument by reference. */
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@ -82,6 +111,9 @@ v850_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
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{
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unsigned HOST_WIDE_INT size;
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if (!TARGET_GCC_ABI)
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return 0;
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if (type)
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size = int_size_in_bytes (type);
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else
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@ -90,14 +122,6 @@ v850_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
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return size > 8;
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}
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/* Implementing the Varargs Macros. */
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static bool
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v850_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
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{
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return !TARGET_GHS ? true : false;
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}
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/* Return an RTX to represent where an argument with mode MODE
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and type TYPE will be passed to a function. If the result
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is NULL_RTX, the argument will be pushed. */
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@ -127,7 +151,9 @@ v850_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
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return NULL_RTX;
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}
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if (size <= UNITS_PER_WORD && type)
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if (!TARGET_GCC_ABI)
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align = UNITS_PER_WORD;
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else if (size <= UNITS_PER_WORD && type)
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align = TYPE_ALIGN (type) / BITS_PER_UNIT;
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else
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align = size;
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@ -171,7 +197,7 @@ v850_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
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CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
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int size, align;
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if (TARGET_GHS && !named)
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if (!named)
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return 0;
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if (mode == BLKmode)
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@ -182,7 +208,9 @@ v850_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
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if (size < 1)
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size = 1;
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if (type)
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if (!TARGET_GCC_ABI)
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align = UNITS_PER_WORD;
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else if (type)
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align = TYPE_ALIGN (type) / BITS_PER_UNIT;
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else
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align = size;
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@ -212,12 +240,18 @@ v850_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
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{
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CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
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cum->nbytes += (((type && int_size_in_bytes (type) > 8
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? GET_MODE_SIZE (Pmode)
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: (mode != BLKmode
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? GET_MODE_SIZE (mode)
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: int_size_in_bytes (type))) + UNITS_PER_WORD - 1)
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& -UNITS_PER_WORD);
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if (!TARGET_GCC_ABI)
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cum->nbytes += (((mode != BLKmode
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? GET_MODE_SIZE (mode)
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: int_size_in_bytes (type)) + UNITS_PER_WORD - 1)
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& -UNITS_PER_WORD);
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else
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cum->nbytes += (((type && int_size_in_bytes (type) > 8
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? GET_MODE_SIZE (Pmode)
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: (mode != BLKmode
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? GET_MODE_SIZE (mode)
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: int_size_in_bytes (type))) + UNITS_PER_WORD - 1)
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& -UNITS_PER_WORD);
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}
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/* Return the high and low words of a CONST_DOUBLE */
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@ -517,8 +551,25 @@ v850_print_operand (FILE * file, rtx x, int code)
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fprintf (file, "[r0]");
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break;
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default:
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case CONST_INT:
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{
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unsigned HOST_WIDE_INT v = INTVAL (x);
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/* Trickery to avoid problems with shifting
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32-bits at a time on a 32-bit host. */
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v = v >> 16;
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v = v >> 16;
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fprintf (file, HOST_WIDE_INT_PRINT_HEX, v);
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break;
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}
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case CONST_DOUBLE:
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fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
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break;
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default:
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debug_rtx (x);
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gcc_unreachable ();
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}
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break;
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case 'S':
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@ -583,6 +634,10 @@ v850_print_operand (FILE * file, rtx x, int code)
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case SUBREG:
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fputs (reg_names[subreg_regno (x)], file);
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break;
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case CONST_DOUBLE:
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fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
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break;
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case CONST_INT:
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case SYMBOL_REF:
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case CONST:
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@ -895,7 +950,7 @@ v850_float_nz_comparison_operator (rtx op, enum machine_mode mode)
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_NEmode)
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return code == NE;
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return 0;
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return code == GT || code == GE || code == NE;
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}
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enum machine_mode
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@ -1287,7 +1342,7 @@ v850_reorg (void)
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case INSN:
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pattern = single_set (insn);
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/* See if there are any memory references we can shorten */
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/* See if there are any memory references we can shorten. */
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if (pattern)
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{
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rtx src = SET_SRC (pattern);
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@ -1301,11 +1356,11 @@ v850_reorg (void)
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if (GET_CODE (dest) == SUBREG
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&& (GET_CODE (SUBREG_REG (dest)) == MEM
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|| GET_CODE (SUBREG_REG (dest)) == REG))
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alter_subreg (&dest, true);
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alter_subreg (&dest, false);
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if (GET_CODE (src) == SUBREG
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&& (GET_CODE (SUBREG_REG (src)) == MEM
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|| GET_CODE (SUBREG_REG (src)) == REG))
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alter_subreg (&src, true);
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alter_subreg (&src, false);
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if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
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mem = NULL_RTX;
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@ -1448,13 +1503,6 @@ compute_register_save_size (long * p_reg_saved)
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int call_p = df_regs_ever_live_p (LINK_POINTER_REGNUM);
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long reg_saved = 0;
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/* Always save the link pointer - we cannot rely upon df_regs_ever_live_p. */
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if (!call_p)
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{
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df_set_regs_ever_live (LINK_POINTER_REGNUM, true);
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call_p = 1;
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}
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/* Count space for the register saves. */
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if (interrupt_handler)
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{
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@ -1547,6 +1595,34 @@ compute_register_save_size (long * p_reg_saved)
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return size;
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}
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/* Typical stack layout should looks like this after the function's prologue:
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| |
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-- ^
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| | \ |
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| | arguments saved | Increasing
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| | on the stack | addresses
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PARENT arg pointer -> | | /
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-------------------------- ---- -------------------
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| | - space for argument split between regs & stack
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--
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CHILD | | \ <-- (return address here)
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| | other call
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| | saved registers
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| | /
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--
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frame pointer -> | | \ ___
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| | local |
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| | variables |f
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| | / |r
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-- |a
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| | \ |m
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| | outgoing |e
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| | arguments | | Decreasing
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(hard) frame pointer | | / | | addresses
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and stack pointer -> | | / _|_ |
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-------------------------- ---- ------------------ V */
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int
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compute_frame_size (int size, long * p_reg_saved)
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{
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@ -1590,7 +1666,7 @@ use_prolog_function (int num_save, int frame_size)
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}
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static void
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increment_stack (unsigned int amount)
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increment_stack (signed int amount, bool in_prologue)
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{
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rtx inc;
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@ -1603,11 +1679,15 @@ increment_stack (unsigned int amount)
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{
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rtx reg = gen_rtx_REG (Pmode, 12);
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emit_move_insn (reg, inc);
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inc = emit_move_insn (reg, inc);
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if (in_prologue)
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F (inc);
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inc = reg;
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}
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emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, inc));
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inc = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, inc));
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if (in_prologue)
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F (inc);
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}
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void
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|
@ -1641,6 +1721,10 @@ expand_prologue (void)
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if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
|
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actual_fsize -= INTERRUPT_ALL_SAVE_SIZE;
|
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|
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/* Interrupt functions are not passed arguments, so no need to
|
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allocate space for split structure arguments. */
|
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gcc_assert (crtl->args.pretend_args_size == 0);
|
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}
|
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|
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/* Identify all of the saved registers. */
|
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|
|
@ -1651,10 +1735,25 @@ expand_prologue (void)
|
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save_regs[num_save++] = gen_rtx_REG (Pmode, i);
|
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}
|
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|
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if (crtl->args.pretend_args_size)
|
||||
{
|
||||
if (num_save == 0)
|
||||
{
|
||||
increment_stack (- (actual_fsize + crtl->args.pretend_args_size), true);
|
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actual_fsize = 0;
|
||||
}
|
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else
|
||||
increment_stack (- crtl->args.pretend_args_size, true);
|
||||
}
|
||||
|
||||
/* See if we have an insn that allocates stack space and saves the particular
|
||||
registers we want to. */
|
||||
registers we want to. Note that the helpers won't
|
||||
allocate additional space for registers GCC saves to complete a
|
||||
"split" structure argument. */
|
||||
save_all = NULL_RTX;
|
||||
if (TARGET_PROLOG_FUNCTION && num_save > 0)
|
||||
if (TARGET_PROLOG_FUNCTION
|
||||
&& !crtl->args.pretend_args_size
|
||||
&& num_save > 0)
|
||||
{
|
||||
if (use_prolog_function (num_save, actual_fsize))
|
||||
{
|
||||
|
|
@ -1694,6 +1793,8 @@ expand_prologue (void)
|
|||
= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
|
||||
}
|
||||
|
||||
v850_all_frame_related (save_all);
|
||||
|
||||
code = recog (save_all, NULL_RTX, NULL);
|
||||
if (code >= 0)
|
||||
{
|
||||
|
|
@ -1734,26 +1835,26 @@ expand_prologue (void)
|
|||
offset = init_stack_alloc - 4;
|
||||
|
||||
if (init_stack_alloc)
|
||||
increment_stack (- (signed) init_stack_alloc);
|
||||
increment_stack (- (signed) init_stack_alloc, true);
|
||||
|
||||
/* Save the return pointer first. */
|
||||
if (num_save > 0 && REGNO (save_regs[num_save-1]) == LINK_POINTER_REGNUM)
|
||||
{
|
||||
emit_move_insn (gen_rtx_MEM (SImode,
|
||||
plus_constant (Pmode,
|
||||
stack_pointer_rtx,
|
||||
offset)),
|
||||
save_regs[--num_save]);
|
||||
F (emit_move_insn (gen_rtx_MEM (SImode,
|
||||
plus_constant (Pmode,
|
||||
stack_pointer_rtx,
|
||||
offset)),
|
||||
save_regs[--num_save]));
|
||||
offset -= 4;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_save; i++)
|
||||
{
|
||||
emit_move_insn (gen_rtx_MEM (SImode,
|
||||
plus_constant (Pmode,
|
||||
stack_pointer_rtx,
|
||||
offset)),
|
||||
save_regs[i]);
|
||||
F (emit_move_insn (gen_rtx_MEM (SImode,
|
||||
plus_constant (Pmode,
|
||||
stack_pointer_rtx,
|
||||
offset)),
|
||||
save_regs[i]));
|
||||
offset -= 4;
|
||||
}
|
||||
}
|
||||
|
|
@ -1763,15 +1864,11 @@ expand_prologue (void)
|
|||
> 32K or we just called a function to save the registers and needed more
|
||||
stack. */
|
||||
if (actual_fsize > init_stack_alloc)
|
||||
{
|
||||
int diff = actual_fsize - init_stack_alloc;
|
||||
|
||||
increment_stack (- diff);
|
||||
}
|
||||
increment_stack (init_stack_alloc - actual_fsize, true);
|
||||
|
||||
/* If we need a frame pointer, set it up now. */
|
||||
if (frame_pointer_needed)
|
||||
emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
|
||||
F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1814,6 +1911,7 @@ expand_epilogue (void)
|
|||
|
||||
if (TARGET_PROLOG_FUNCTION
|
||||
&& num_restore > 0
|
||||
&& !crtl->args.pretend_args_size
|
||||
&& !interrupt_handler)
|
||||
{
|
||||
int alloc_stack = (4 * num_restore);
|
||||
|
|
@ -1851,7 +1949,7 @@ expand_epilogue (void)
|
|||
rtx insn;
|
||||
|
||||
actual_fsize -= alloc_stack;
|
||||
increment_stack (actual_fsize);
|
||||
increment_stack (actual_fsize, false);
|
||||
|
||||
insn = emit_jump_insn (restore_all);
|
||||
INSN_CODE (insn) = code;
|
||||
|
|
@ -1877,7 +1975,7 @@ expand_epilogue (void)
|
|||
|
||||
/* Deallocate the rest of the stack if it is > 32K. */
|
||||
if ((unsigned int) actual_fsize > init_stack_free)
|
||||
increment_stack (actual_fsize - init_stack_free);
|
||||
increment_stack (actual_fsize - init_stack_free, false);
|
||||
|
||||
/* Special case interrupt functions that save all registers
|
||||
for a call. */
|
||||
|
|
@ -1918,7 +2016,8 @@ expand_epilogue (void)
|
|||
}
|
||||
|
||||
/* Cut back the remainder of the stack. */
|
||||
increment_stack (init_stack_free);
|
||||
increment_stack (init_stack_free + crtl->args.pretend_args_size,
|
||||
false);
|
||||
}
|
||||
|
||||
/* And return or use reti for interrupt handlers. */
|
||||
|
|
@ -2931,7 +3030,11 @@ static bool
|
|||
v850_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Return values > 8 bytes in length in memory. */
|
||||
return int_size_in_bytes (type) > 8 || TYPE_MODE (type) == BLKmode;
|
||||
return int_size_in_bytes (type) > 8
|
||||
|| TYPE_MODE (type) == BLKmode
|
||||
/* With the rh850 ABI return all aggregates in memory. */
|
||||
|| ((! TARGET_GCC_ABI) && AGGREGATE_TYPE_P (type))
|
||||
;
|
||||
}
|
||||
|
||||
/* Worker function for TARGET_FUNCTION_VALUE. */
|
||||
|
|
@ -2945,18 +3048,6 @@ v850_function_value (const_tree valtype,
|
|||
}
|
||||
|
||||
|
||||
/* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
|
||||
|
||||
static void
|
||||
v850_setup_incoming_varargs (cumulative_args_t ca,
|
||||
enum machine_mode mode ATTRIBUTE_UNUSED,
|
||||
tree type ATTRIBUTE_UNUSED,
|
||||
int *pretend_arg_size ATTRIBUTE_UNUSED,
|
||||
int second_time ATTRIBUTE_UNUSED)
|
||||
{
|
||||
get_cumulative_args (ca)->anonymous_args = (!TARGET_GHS ? 1 : 0);
|
||||
}
|
||||
|
||||
/* Worker function for TARGET_CAN_ELIMINATE. */
|
||||
|
||||
static bool
|
||||
|
|
@ -3067,29 +3158,35 @@ static const struct attribute_spec v850_attribute_table[] =
|
|||
{ NULL, 0, 0, false, false, false, NULL, false }
|
||||
};
|
||||
|
||||
static enum unwind_info_type
|
||||
v850_debug_unwind_info (void)
|
||||
{
|
||||
return UI_NONE;
|
||||
}
|
||||
|
||||
#undef TARGET_DEBUG_UNWIND_INFO
|
||||
#define TARGET_DEBUG_UNWIND_INFO v850_debug_unwind_info
|
||||
static void
|
||||
v850_option_override (void)
|
||||
{
|
||||
if (flag_exceptions || flag_non_call_exceptions)
|
||||
flag_omit_frame_pointer = 0;
|
||||
|
||||
/* The RH850 ABI does not (currently) support the use of the CALLT instruction. */
|
||||
if (! TARGET_GCC_ABI)
|
||||
target_flags |= MASK_DISABLE_CALLT;
|
||||
}
|
||||
|
||||
/* Initialize the GCC target structure. */
|
||||
|
||||
#undef TARGET_OPTION_OVERRIDE
|
||||
#define TARGET_OPTION_OVERRIDE v850_option_override
|
||||
|
||||
#undef TARGET_MEMORY_MOVE_COST
|
||||
#define TARGET_MEMORY_MOVE_COST v850_memory_move_cost
|
||||
#define TARGET_MEMORY_MOVE_COST v850_memory_move_cost
|
||||
|
||||
#undef TARGET_ASM_ALIGNED_HI_OP
|
||||
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
|
||||
|
||||
#undef TARGET_PRINT_OPERAND
|
||||
#define TARGET_PRINT_OPERAND v850_print_operand
|
||||
#define TARGET_PRINT_OPERAND v850_print_operand
|
||||
#undef TARGET_PRINT_OPERAND_ADDRESS
|
||||
#define TARGET_PRINT_OPERAND_ADDRESS v850_print_operand_address
|
||||
#define TARGET_PRINT_OPERAND_ADDRESS v850_print_operand_address
|
||||
#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
|
||||
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P v850_print_operand_punct_valid_p
|
||||
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P v850_print_operand_punct_valid_p
|
||||
|
||||
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
|
||||
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA v850_output_addr_const_extra
|
||||
|
|
@ -3143,9 +3240,6 @@ v850_debug_unwind_info (void)
|
|||
#undef TARGET_CALLEE_COPIES
|
||||
#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
|
||||
|
||||
#undef TARGET_SETUP_INCOMING_VARARGS
|
||||
#define TARGET_SETUP_INCOMING_VARARGS v850_setup_incoming_varargs
|
||||
|
||||
#undef TARGET_ARG_PARTIAL_BYTES
|
||||
#define TARGET_ARG_PARTIAL_BYTES v850_arg_partial_bytes
|
||||
|
||||
|
|
@ -3166,9 +3260,6 @@ v850_debug_unwind_info (void)
|
|||
#undef TARGET_TRAMPOLINE_INIT
|
||||
#define TARGET_TRAMPOLINE_INIT v850_trampoline_init
|
||||
|
||||
#undef TARGET_STRICT_ARGUMENT_NAMING
|
||||
#define TARGET_STRICT_ARGUMENT_NAMING v850_strict_argument_naming
|
||||
|
||||
#undef TARGET_LEGITIMATE_CONSTANT_P
|
||||
#define TARGET_LEGITIMATE_CONSTANT_P v850_legitimate_constant_p
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Definitions of target machine for GNU compiler. NEC V850 series
|
||||
Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
|
||||
2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
|
||||
2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
|
||||
Contributed by Jeff Law (law@cygnus.com).
|
||||
|
||||
This file is part of GCC.
|
||||
|
|
@ -89,7 +89,13 @@ extern GTY(()) rtx v850_compare_op1;
|
|||
|
||||
#define TARGET_V850E2_ALL (TARGET_V850E2 || TARGET_V850E2V3)
|
||||
|
||||
#define ASM_SPEC "%{mv850es:-mv850e1}%{!mv850es:%{mv*:-mv%*}}"
|
||||
#define ASM_SPEC "%{m850es:-mv850e1}%{!mv850es:%{mv*:-mv%*}} \
|
||||
%{mrelax:-mrelax} \
|
||||
%{m8byte-align:-m8byte-align} \
|
||||
%{mgcc-abi:-mgcc-abi}"
|
||||
|
||||
#define LINK_SPEC "%{mgcc-abi:-m v850}"
|
||||
|
||||
#define CPP_SPEC "\
|
||||
%{mv850e2v3:-D__v850e2v3__} \
|
||||
%{mv850e2:-D__v850e2__} \
|
||||
|
|
@ -104,15 +110,32 @@ extern GTY(()) rtx v850_compare_op1;
|
|||
{ "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
|
||||
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }
|
||||
|
||||
/* Names to predefine in the preprocessor for this target machine. */
|
||||
#define TARGET_CPU_CPP_BUILTINS() do { \
|
||||
builtin_define( "__v851__" ); \
|
||||
builtin_define( "__v850" ); \
|
||||
builtin_assert( "machine=v850" ); \
|
||||
builtin_assert( "cpu=v850" ); \
|
||||
if (TARGET_EP) \
|
||||
builtin_define ("__EP__"); \
|
||||
} while(0)
|
||||
|
||||
/* Macro to decide when FPU instructions can be used. */
|
||||
#define TARGET_USE_FPU (TARGET_V850E2V3 && ! TARGET_SOFT_FLOAT)
|
||||
|
||||
#define TARGET_CPU_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_define( "__v851__" ); \
|
||||
builtin_define( "__v850" ); \
|
||||
builtin_define( "__v850__" ); \
|
||||
builtin_assert( "machine=v850" ); \
|
||||
builtin_assert( "cpu=v850" ); \
|
||||
if (TARGET_EP) \
|
||||
builtin_define ("__EP__"); \
|
||||
if (TARGET_GCC_ABI) \
|
||||
builtin_define ("__V850_GCC_ABI__"); \
|
||||
else \
|
||||
builtin_define ("__V850_RH850_ABI__"); \
|
||||
if (! TARGET_DISABLE_CALLT) \
|
||||
builtin_define ("__V850_CALLT__"); \
|
||||
if (TARGET_8BYTE_ALIGN) \
|
||||
builtin_define ("__V850_8BYTE_ALIGN__");\
|
||||
builtin_define (TARGET_USE_FPU ? \
|
||||
"__FPU_OK__" : "__NO_FPU__");\
|
||||
} \
|
||||
while(0)
|
||||
|
||||
#define MASK_CPU (MASK_V850 | MASK_V850E | MASK_V850E1 | MASK_V850E2 | MASK_V850E2V3)
|
||||
|
||||
|
|
@ -153,20 +176,20 @@ extern GTY(()) rtx v850_compare_op1;
|
|||
#define PARM_BOUNDARY 32
|
||||
|
||||
/* The stack goes in 32-bit lumps. */
|
||||
#define STACK_BOUNDARY 32
|
||||
#define STACK_BOUNDARY BIGGEST_ALIGNMENT
|
||||
|
||||
/* Allocation boundary (in *bits*) for the code of a function.
|
||||
16 is the minimum boundary; 32 would give better performance. */
|
||||
#define FUNCTION_BOUNDARY (optimize_size ? 16 : 32)
|
||||
#define FUNCTION_BOUNDARY (((! TARGET_GCC_ABI) || optimize_size) ? 16 : 32)
|
||||
|
||||
/* No data type wants to be aligned rounder than this. */
|
||||
#define BIGGEST_ALIGNMENT 32
|
||||
#define BIGGEST_ALIGNMENT (TARGET_8BYTE_ALIGN ? 64 : 32)
|
||||
|
||||
/* Alignment of field after `int : 0' in a structure. */
|
||||
#define EMPTY_FIELD_BOUNDARY 32
|
||||
|
||||
/* No structure field wants to be aligned rounder than this. */
|
||||
#define BIGGEST_FIELD_ALIGNMENT 32
|
||||
#define BIGGEST_FIELD_ALIGNMENT BIGGEST_ALIGNMENT
|
||||
|
||||
/* Define this if move instructions will actually fail to work
|
||||
when given unaligned data. */
|
||||
|
|
@ -291,7 +314,7 @@ extern GTY(()) rtx v850_compare_op1;
|
|||
|
||||
enum reg_class
|
||||
{
|
||||
NO_REGS, GENERAL_REGS, EVEN_REGS, ALL_REGS, LIM_REG_CLASSES
|
||||
NO_REGS, EVEN_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
|
||||
};
|
||||
|
||||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||||
|
|
@ -299,7 +322,7 @@ enum reg_class
|
|||
/* Give names of register classes as strings for dump file. */
|
||||
|
||||
#define REG_CLASS_NAMES \
|
||||
{ "NO_REGS", "GENERAL_REGS", "EVEN_REGS", "ALL_REGS", "LIM_REGS" }
|
||||
{ "NO_REGS", "EVEN_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
|
||||
|
||||
/* Define which registers fit in which classes.
|
||||
This is an initializer for a vector of HARD_REG_SET
|
||||
|
|
@ -308,8 +331,8 @@ enum reg_class
|
|||
#define REG_CLASS_CONTENTS \
|
||||
{ \
|
||||
{ 0x00000000,0x0 }, /* NO_REGS */ \
|
||||
{ 0xffffffff,0x0 }, /* GENERAL_REGS */ \
|
||||
{ 0x55555554,0x0 }, /* EVEN_REGS */ \
|
||||
{ 0xfffffffe,0x0 }, /* GENERAL_REGS */ \
|
||||
{ 0xffffffff,0x0 }, /* ALL_REGS */ \
|
||||
}
|
||||
|
||||
|
|
@ -485,14 +508,14 @@ enum reg_class
|
|||
such as FUNCTION_ARG to determine where the next arg should go. */
|
||||
|
||||
#define CUMULATIVE_ARGS struct cum_arg
|
||||
struct cum_arg { int nbytes; int anonymous_args; };
|
||||
struct cum_arg { int nbytes; };
|
||||
|
||||
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
||||
for a call to a function whose data type is FNTYPE.
|
||||
For a library call, FNTYPE is 0. */
|
||||
|
||||
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
||||
((CUM).nbytes = 0, (CUM).anonymous_args = 0)
|
||||
do { (CUM).nbytes = 0; } while (0)
|
||||
|
||||
/* When a parameter is passed in a register, stack space is still
|
||||
allocated for it. */
|
||||
|
|
@ -785,10 +808,14 @@ typedef enum
|
|||
/* We don't have to worry about dbx compatibility for the v850. */
|
||||
#define DEFAULT_GDB_EXTENSIONS 1
|
||||
|
||||
/* Use stabs debugging info by default. */
|
||||
/* Use dwarf2 debugging info by default. */
|
||||
#undef PREFERRED_DEBUGGING_TYPE
|
||||
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
|
||||
#define DBX_DEBUGGING_INFO 1
|
||||
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
||||
|
||||
#define DWARF2_FRAME_INFO 1
|
||||
#define DWARF2_UNWIND_INFO 0
|
||||
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_POINTER_REGNUM)
|
||||
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_POINTER_REGNUM)
|
||||
|
||||
#ifndef ASM_GENERATE_INTERNAL_LABEL
|
||||
#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
;; GCC machine description for NEC V850
|
||||
;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010
|
||||
;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010, 2012
|
||||
;; Free Software Foundation, Inc.
|
||||
;; Contributed by Jeff Law (law@cygnus.com).
|
||||
|
||||
|
|
@ -409,7 +409,7 @@
|
|||
[(set (reg:CC CC_REGNUM)
|
||||
(compare (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
{
|
||||
v850_compare_op0 = operands[0];
|
||||
v850_compare_op1 = operands[1];
|
||||
|
|
@ -420,7 +420,7 @@
|
|||
[(set (reg:CC CC_REGNUM)
|
||||
(compare (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
{
|
||||
v850_compare_op0 = operands[0];
|
||||
v850_compare_op1 = operands[1];
|
||||
|
|
@ -1764,7 +1764,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(plus:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"addf.s %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1774,7 +1774,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(plus:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"addf.d %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1784,7 +1784,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(minus:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"subf.s %2,%1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1794,7 +1794,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(minus:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"subf.d %2,%1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1804,7 +1804,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(mult:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"mulf.s %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1814,7 +1814,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(mult:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"mulf.d %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1824,7 +1824,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(div:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"divf.s %2,%1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1834,7 +1834,7 @@
|
|||
[(set (match_operand:DF 0 "register_operand" "=r")
|
||||
(div:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"divf.d %2,%1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1844,7 +1844,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(smin:SF (match_operand:SF 1 "reg_or_0_operand" "r")
|
||||
(match_operand:SF 2 "reg_or_0_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"minf.s %z1,%z2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1854,7 +1854,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(smin:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"minf.d %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1864,7 +1864,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(smax:SF (match_operand:SF 1 "reg_or_0_operand" "r")
|
||||
(match_operand:SF 2 "reg_or_0_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"maxf.s %z1,%z2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1874,7 +1874,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(smax:DF (match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"maxf.d %1,%2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1883,7 +1883,7 @@
|
|||
(define_insn "abssf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(abs:SF (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"absf.s %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1892,7 +1892,7 @@
|
|||
(define_insn "absdf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(abs:DF (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"absf.d %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1901,7 +1901,7 @@
|
|||
(define_insn "negsf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(neg:SF (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"negf.s %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1910,7 +1910,7 @@
|
|||
(define_insn "negdf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(neg:DF (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"negf.d %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1920,7 +1920,7 @@
|
|||
(define_insn "sqrtsf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"sqrtf.s %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1929,7 +1929,7 @@
|
|||
(define_insn "sqrtdf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"sqrtf.d %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1939,56 +1939,158 @@
|
|||
(define_insn "fix_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.sw %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "fixuns_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.suw %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")]
|
||||
)
|
||||
|
||||
(define_insn "fix_truncdfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.dw %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_expand "fixuns_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3")
|
||||
(define_insn "fixuns_truncdfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unsigned_fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.duw %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")]
|
||||
)
|
||||
|
||||
(define_expand "fixuns_truncdfsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3")
|
||||
(define_insn "fix_truncsfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(fix:DI (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.sl %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "fixuns_truncsfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.sul %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")]
|
||||
)
|
||||
|
||||
(define_insn "fix_truncdfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.dl %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "fixuns_truncdfdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unsigned_fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"trncf.dul %1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")]
|
||||
)
|
||||
|
||||
;; int -> float
|
||||
(define_insn "floatsisf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.ws %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "unsfloatsisf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.uws %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "floatsidf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.wd %z1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "unsfloatsidf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.uwd %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "floatdisf2"
|
||||
[(set (match_operand:SF 0 "even_reg_operand" "=r")
|
||||
(float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.ls %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "unsfloatdisf2"
|
||||
[(set (match_operand:SF 0 "even_reg_operand" "=r")
|
||||
(unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.uls %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "floatdidf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.ld %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "unsfloatdidf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.uld %z1, %0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
;; single-float -> double-float
|
||||
(define_insn "extendsfdf2"
|
||||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(float_extend:DF
|
||||
(match_operand:SF 1 "reg_or_0_operand" "rI")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.sd %z1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -1999,7 +2101,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cvtf.ds %1,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2014,7 +2116,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
|
||||
(match_operand:SF 2 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"recipf.s %2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2024,7 +2126,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"recipf.d %2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2035,7 +2137,7 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
|
||||
(sqrt:SF (match_operand:SF 2 "register_operand" "r"))))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"rsqrtf.s %2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2045,7 +2147,7 @@
|
|||
[(set (match_operand:DF 0 "even_reg_operand" "=r")
|
||||
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
|
||||
(sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"rsqrtf.d %2,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2057,7 +2159,7 @@
|
|||
(fma:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(match_operand:SF 3 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"maddf.s %2,%1,%3,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2069,7 +2171,7 @@
|
|||
(fma:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"msubf.s %2,%1,%3,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2078,10 +2180,10 @@
|
|||
;;; negative-multiply-add
|
||||
(define_insn "fnmasf4"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(match_operand:SF 3 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
(neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(match_operand:SF 3 "register_operand" "r"))))]
|
||||
"TARGET_USE_FPU"
|
||||
"nmaddf.s %2,%1,%3,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2090,10 +2192,10 @@
|
|||
;; negative-multiply-subtract
|
||||
(define_insn "fnmssf4"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
|
||||
"TARGET_V850E2V3"
|
||||
(neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
|
||||
(match_operand:SF 2 "register_operand" "r")
|
||||
(neg:SF (match_operand:SF 3 "register_operand" "r")))))]
|
||||
"TARGET_USE_FPU"
|
||||
"nmsubf.s %2,%1,%3,%0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
|
|
@ -2107,8 +2209,8 @@
|
|||
[(set (reg:CC_FPU_LE FCC_REGNUM)
|
||||
(compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s le,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s le,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2117,8 +2219,8 @@
|
|||
[(set (reg:CC_FPU_LT FCC_REGNUM)
|
||||
(compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s lt,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s lt,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2127,8 +2229,8 @@
|
|||
[(set (reg:CC_FPU_GE FCC_REGNUM)
|
||||
(compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s ge,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s ge,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2137,8 +2239,8 @@
|
|||
[(set (reg:CC_FPU_GT FCC_REGNUM)
|
||||
(compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s gt,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s gt,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2147,8 +2249,8 @@
|
|||
[(set (reg:CC_FPU_EQ FCC_REGNUM)
|
||||
(compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s eq,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s eq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2157,8 +2259,8 @@
|
|||
[(set (reg:CC_FPU_NE FCC_REGNUM)
|
||||
(compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.s neq,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s neq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2169,8 +2271,8 @@
|
|||
[(set (reg:CC_FPU_LE FCC_REGNUM)
|
||||
(compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d le,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d le,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2179,8 +2281,8 @@
|
|||
[(set (reg:CC_FPU_LT FCC_REGNUM)
|
||||
(compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d lt,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d lt,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2189,8 +2291,8 @@
|
|||
[(set (reg:CC_FPU_GE FCC_REGNUM)
|
||||
(compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d ge,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d ge,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2199,8 +2301,8 @@
|
|||
[(set (reg:CC_FPU_GT FCC_REGNUM)
|
||||
(compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d gt,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d gt,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2209,8 +2311,8 @@
|
|||
[(set (reg:CC_FPU_EQ FCC_REGNUM)
|
||||
(compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d eq,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d eq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2219,8 +2321,8 @@
|
|||
[(set (reg:CC_FPU_NE FCC_REGNUM)
|
||||
(compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"cmpf.d neq,%z0,%z1"
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d neq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2233,7 +2335,7 @@
|
|||
|
||||
(define_insn "trfsr"
|
||||
[(set (match_operand 0 "" "") (match_operand 1 "" ""))]
|
||||
"TARGET_V850E2V3
|
||||
"TARGET_USE_FPU
|
||||
&& GET_MODE(operands[0]) == GET_MODE(operands[1])
|
||||
&& GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
|
||||
&& GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
|
||||
|
|
@ -2260,7 +2362,7 @@
|
|||
(match_operand 3 "v850_float_z_comparison_operator" "")
|
||||
(match_operand:SF 1 "reg_or_0_operand" "rIG")
|
||||
(match_operand:SF 2 "reg_or_0_operand" "rIG")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.s 0,%z1,%z2,%0"
|
||||
[(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
||||
|
|
@ -2270,7 +2372,7 @@
|
|||
(match_operand 3 "v850_float_nz_comparison_operator" "")
|
||||
(match_operand:SF 1 "reg_or_0_operand" "rIG")
|
||||
(match_operand:SF 2 "reg_or_0_operand" "rIG")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.s 0,%z2,%z1,%0"
|
||||
[(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
||||
|
|
@ -2280,7 +2382,7 @@
|
|||
(match_operand 3 "v850_float_z_comparison_operator" "")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.d 0,%z1,%z2,%0"
|
||||
[(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
||||
|
|
@ -2290,7 +2392,7 @@
|
|||
(match_operand 3 "v850_float_nz_comparison_operator" "")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")
|
||||
(match_operand:DF 2 "even_reg_operand" "r")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.d 0,%z2,%z1,%0"
|
||||
[(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
||||
|
|
@ -2300,7 +2402,7 @@
|
|||
(match_operand 3 "v850_float_z_comparison_operator" "")
|
||||
(match_operand:DF 1 "reg_or_0_operand" "rIG")
|
||||
(match_operand:DF 2 "reg_or_0_operand" "rIG")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
|
@ -2311,7 +2413,7 @@
|
|||
(match_operand 3 "v850_float_nz_comparison_operator" "")
|
||||
(match_operand:DF 1 "reg_or_0_operand" "rIG")
|
||||
(match_operand:DF 2 "reg_or_0_operand" "rIG")))]
|
||||
"TARGET_V850E2V3"
|
||||
"TARGET_USE_FPU"
|
||||
"cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cc" "clobber")]) ;; ??? or none_0hit
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
; Options for the NEC V850 port of the compiler.
|
||||
|
||||
; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
|
||||
; Copyright (C) 2005, 2007, 2010, 2011, 2012 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
|
|
@ -38,15 +38,14 @@ Enable backend debugging
|
|||
|
||||
mdisable-callt
|
||||
Target Report Mask(DISABLE_CALLT)
|
||||
Do not use the callt instruction
|
||||
Do not use the callt instruction (default)
|
||||
|
||||
mep
|
||||
Target Report Mask(EP)
|
||||
Reuse r30 on a per function basis
|
||||
|
||||
mghs
|
||||
Target Report Mask(GHS)
|
||||
Support Green Hills ABI
|
||||
Target RejectNegative InverseMask(GCC_ABI) MaskExists
|
||||
|
||||
mlong-calls
|
||||
Target Report Mask(LONG_CALLS)
|
||||
|
|
@ -119,3 +118,31 @@ Set the max size of data eligible for the ZDA area
|
|||
|
||||
mzda-
|
||||
Target RejectNegative Joined Undocumented Alias(mzda=)
|
||||
|
||||
mrelax
|
||||
Target Report Mask(RELAX)
|
||||
Enable relaxing in the assembler
|
||||
|
||||
mlong-jumps
|
||||
Target Report Mask(BIG_SWITCH) MaskExists
|
||||
Prohibit PC relative jumps
|
||||
|
||||
msoft-float
|
||||
Target Report RejectNegative Mask(SOFT_FLOAT)
|
||||
Inhibit the use of hardware floating point instructions
|
||||
|
||||
mhard-float
|
||||
Target Report RejectNegative InverseMask(SOFT_FLOAT) MaskExists
|
||||
Allow the use of hardware floating point instructions for V850E2V3 and up
|
||||
|
||||
mrh850-abi
|
||||
Target RejectNegative Report InverseMask(GCC_ABI) MaskExists
|
||||
Enable support for the RH850 ABI. This is the default
|
||||
|
||||
mgcc-abi
|
||||
Target RejectNegative Report Mask(GCC_ABI)
|
||||
Enable support for the old GCC ABI
|
||||
|
||||
m8byte-align
|
||||
Target Report Mask(8BYTE_ALIGN)
|
||||
Support alignments of up to 64-bits
|
||||
|
|
|
|||
Loading…
Reference in New Issue