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[Patch ARM AARCH64] Split "type" attributes: fdiv 

gcc/
	* config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>.
	* config/arm/arm.md (core_cycles): Remove fdiv.
	* config/arm/vfp.md:
	(*sqrtsf2_vfp): Update for attribute changes.
	(*sqrtdf2_vfp): Likewise.
	* config/aarch64/aarch64.md:
	(sqrt<mode>2): Update for attribute changes.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

From-SVN: r202329
This commit is contained in:
James Greenhalgh 2013-09-06 13:39:57 +00:00 committed by James Greenhalgh
parent 7b49c9e1c0
commit b86923f0cd
16 changed files with 48 additions and 25 deletions
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21
gcc/ChangeLog
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@ -1,3 +1,24 @@
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>.
* config/arm/arm.md (core_cycles): Remove fdiv.
* config/arm/vfp.md:
(*sqrtsf2_vfp): Update for attribute changes.
(*sqrtdf2_vfp): Likewise.
* config/aarch64/aarch64.md:
(sqrt<mode>2): Update for attribute changes.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md

2
gcc/config/aarch64/aarch64.md
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@ -3903,7 +3903,7 @@
"TARGET_FLOAT"
"fsqrt\\t%<s>0, %<s>1"
[(set_attr "v8type" "fsqrt")
(set_attr "type" "fdiv<s>")
(set_attr "type" "fsqrt<s>")
(set_attr "mode" "<MODE>")]
)

1
gcc/config/arm/arm.md
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@ -335,7 +335,6 @@
alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
fdivd, fdivs,\
wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\

4
gcc/config/arm/arm1020e.md
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@ -299,12 +299,12 @@
(define_insn_reservation "v10_fdivs" 18
(and (eq_attr "vfp10" "yes")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"1020a_e+v10_ds*14")
(define_insn_reservation "v10_fdivd" 32
(and (eq_attr "vfp10" "yes")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"1020a_e+v10_fmac+v10_ds*28")
(define_insn_reservation "v10_floads" 4

4
gcc/config/arm/cortex-a15-neon.md
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@ -501,12 +501,12 @@
(define_insn_reservation "cortex_a15_vfp_divs" 10
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"ca15_issue1,ca15_cx_ik")
(define_insn_reservation "cortex_a15_vfp_divd" 18
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"ca15_issue1,ca15_cx_ik")
;; Define bypasses.

4
gcc/config/arm/cortex-a5.md
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@ -233,14 +233,14 @@
(define_insn_reservation "cortex_a5_fdivs" 14
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
;; ??? Similarly for fdivd.
(define_insn_reservation "cortex_a5_fdivd" 29
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

4
gcc/config/arm/cortex-a53.md
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@ -239,12 +239,12 @@
(define_insn_reservation "cortex_a53_fdivs" 14
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13")
(define_insn_reservation "cortex_a53_fdivd" 29
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

4
gcc/config/arm/cortex-a7.md
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@ -288,12 +288,12 @@
(define_insn_reservation "cortex_a7_fdivs" 16
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
(define_insn_reservation "cortex_a7_fdivd" 31
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

4
gcc/config/arm/cortex-a8-neon.md
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@ -159,12 +159,12 @@
(define_insn_reservation "cortex_a8_vfp_divs" 37
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_a8_vfp,cortex_a8_vfplite*36")
(define_insn_reservation "cortex_a8_vfp_divd" 65
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"cortex_a8_vfp,cortex_a8_vfplite*64")
;; Comparisons can actually take 7 cycles sometimes instead of four,

4
gcc/config/arm/cortex-a9.md
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@ -271,12 +271,12 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
;; Division pipeline description.
(define_insn_reservation "cortex_a9_fdivs" 15
(and (eq_attr "tune" "cortexa9")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
(define_insn_reservation "cortex_a9_fdivd" 25
(and (eq_attr "tune" "cortexa9")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
;; Include Neon pipeline description

2
gcc/config/arm/cortex-m4-fpu.md
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@ -30,7 +30,7 @@
;; Integer instructions following VDIV or VSQRT complete out-of-order.
(define_insn_reservation "cortex_m4_fdivs" 15
(and (eq_attr "tune" "cortexm4")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_m4_ex_v,cortex_m4_v*13")
(define_insn_reservation "cortex_m4_vmov_1" 1

4
gcc/config/arm/cortex-r4f.md
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@ -68,7 +68,7 @@
(define_insn_reservation "cortex_r4_fdivs" 17
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"cortex_r4_issue_ab+cortex_r4_v1,cortex_r4_issue_a+cortex_r4_v1")
(define_insn_reservation "cortex_r4_floads" 2
@ -131,7 +131,7 @@
;; out of order. Chances are this is not a pipelined operation.
(define_insn_reservation "cortex_r4_fdivd" 97
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"cortex_r4_single_issue*3")
(define_insn_reservation "cortex_r4_ffarithd" 2

4
gcc/config/arm/marvell-pj4.md
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@ -193,11 +193,11 @@
(define_insn_reservation "pj4_vfp_divs" 20
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fdivs")) "pj4_is,nothing*2,vissue,vdiv*18,nothing")
(eq_attr "type" "fdivs, fsqrts")) "pj4_is,nothing*2,vissue,vdiv*18,nothing")
(define_insn_reservation "pj4_vfp_divd" 34
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fdivd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing")
(eq_attr "type" "fdivd, fsqrtd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing")
(define_insn_reservation "pj4_vfp_mac" 9
(and (eq_attr "tune" "marvell_pj4")

3
gcc/config/arm/types.md
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@ -79,6 +79,7 @@
; float floating point arithmetic operation.
; fmac[d,s] double/single floating point multiply-accumulate.
; fmul[d,s] double/single floating point multiply.
; fsqrt[d,s] double/single precision floating point square root.
; load_acq load-acquire.
; load_byte load byte(s) from memory to arm registers.
; load1 load 1 word from memory to arm registers.
@ -349,6 +350,8 @@
fmacs,\
fmuld,\
fmuls,\
fsqrts,\
fsqrtd,\
load_acq,\
load_byte,\
load1,\

4
gcc/config/arm/vfp.md
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@ -1077,7 +1077,7 @@
"fsqrts%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fdivs")]
(set_attr "type" "fsqrts")]
)
(define_insn "*sqrtdf2_vfp"
@ -1087,7 +1087,7 @@
"fsqrtd%?\\t%P0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fdivd")]
(set_attr "type" "fsqrtd")]
)

4
gcc/config/arm/vfp11.md
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@ -67,12 +67,12 @@
(define_insn_reservation "vfp_fdivs" 19
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivs"))
(eq_attr "type" "fdivs, fsqrts"))
"ds*15")
(define_insn_reservation "vfp_fdivd" 33
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivd"))
(eq_attr "type" "fdivd, fsqrtd"))
"fmac+ds*29")
;; Moves to/from arm regs also use the load/store pipeline.