i386.md (operations with memory inputs setting flags peephole2): Remove uneeded REG_P checks.
* config/i386/i386.md (operations with memory inputs setting flags peephole2): Remove uneeded REG_P checks. Cleanup pattern generation. From-SVN: r235641
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@ -1,3 +1,9 @@
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2016-04-29 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md
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(operations with memory inputs setting flags peephole2):
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Remove uneeded REG_P checks. Cleanup pattern generation.
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2016-04-29 Ilya Enkovich <ilya.enkovich@intel.com>
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* tree-vect-loop.c (vect_transform_loop): Fix
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@ -12,9 +18,8 @@
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2016-04-29 Andrew Burgess <andrew.burgess@embecosm.com>
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* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
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constraint with 'rCm2' constraints to limit possible immediate
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size.
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* config/arc/arc.md (*loadqi_update): Replace use of 'rI' constraint
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with 'rCm2' constraints to limit possible immediate size.
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(*load_zeroextendqisi_update): Likewise.
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(*load_signextendqisi_update): Likewise.
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(*loadhi_update): Likewise.
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@ -18006,16 +18006,18 @@
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(GET_CODE (operands[3]) == PLUS
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|| GET_CODE (operands[3]) == MINUS)
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? CCGOCmode : CCNOmode)"
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[(parallel [(set (match_dup 4) (match_dup 5))
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(set (match_dup 1) (match_op_dup 3 [(match_dup 1)
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(match_dup 2)]))])]
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[(parallel [(set (match_dup 4) (match_dup 6))
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(set (match_dup 1) (match_dup 5))])]
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{
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operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
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operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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copy_rtx (operands[1]),
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copy_rtx (operands[2]));
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operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
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operands[5], const0_rtx);
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operands[5]
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= gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
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copy_rtx (operands[1]),
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operands[2]);
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operands[6]
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= gen_rtx_COMPARE (GET_MODE (operands[4]),
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copy_rtx (operands[5]),
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const0_rtx);
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})
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;; Likewise for instances where we have a lea pattern.
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@ -18038,16 +18040,18 @@
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|| immediate_operand (operands[2], QImode)
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|| any_QIreg_operand (operands[2], QImode))
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&& ix86_match_ccmode (peep2_next_insn (3), CCGOCmode)"
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[(parallel [(set (match_dup 4) (match_dup 5))
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(set (match_dup 1) (plus:SWI (match_dup 1)
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(match_dup 2)))])]
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[(parallel [(set (match_dup 4) (match_dup 6))
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(set (match_dup 1) (match_dup 5))])]
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{
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operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
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operands[5] = gen_rtx_PLUS (<MODE>mode,
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copy_rtx (operands[1]),
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copy_rtx (operands[2]));
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operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
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operands[5], const0_rtx);
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operands[5]
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= gen_rtx_PLUS (<MODE>mode,
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copy_rtx (operands[1]),
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operands[2]);
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operands[6]
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= gen_rtx_COMPARE (GET_MODE (operands[4]),
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copy_rtx (operands[5]),
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const0_rtx);
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})
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(define_peephole2
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@ -18065,16 +18069,18 @@
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&& ix86_match_ccmode (peep2_next_insn (2),
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GET_CODE (operands[2]) == PLUS
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? CCGOCmode : CCNOmode)"
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[(parallel [(set (match_dup 3) (match_dup 4))
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(set (match_dup 1) (match_op_dup 2 [(match_dup 1)
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(match_dup 0)]))])]
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[(parallel [(set (match_dup 3) (match_dup 5))
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(set (match_dup 1) (match_dup 4))])]
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{
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operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
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copy_rtx (operands[1]),
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copy_rtx (operands[0]));
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operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
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operands[4], const0_rtx);
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operands[4]
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= gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
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copy_rtx (operands[1]),
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operands[0]);
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operands[5]
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= gen_rtx_COMPARE (GET_MODE (operands[3]),
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copy_rtx (operands[4]),
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const0_rtx);
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})
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(define_peephole2
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@ -18088,7 +18094,6 @@
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(set (match_dup 1) (match_dup 0))
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(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
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"(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
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&& REG_P (operands[0]) && REG_P (operands[4])
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&& REGNO (operands[0]) == REGNO (operands[4])
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&& peep2_reg_dead_p (4, operands[0])
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&& (<MODE>mode != QImode
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@ -18100,18 +18105,18 @@
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(GET_CODE (operands[3]) == PLUS
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|| GET_CODE (operands[3]) == MINUS)
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? CCGOCmode : CCNOmode)"
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[(parallel [(set (match_dup 4) (match_dup 5))
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(set (match_dup 1) (match_dup 6))])]
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[(parallel [(set (match_dup 4) (match_dup 6))
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(set (match_dup 1) (match_dup 5))])]
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{
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operands[2] = gen_lowpart (<MODE>mode, operands[2]);
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operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
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operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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copy_rtx (operands[1]), operands[2]);
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operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
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operands[5], const0_rtx);
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operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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copy_rtx (operands[1]),
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copy_rtx (operands[2]));
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operands[5]
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= gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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copy_rtx (operands[1]),
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gen_lowpart (<MODE>mode, operands[2]));
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operands[6]
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= gen_rtx_COMPARE (GET_MODE (operands[4]),
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copy_rtx (operands[5]),
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const0_rtx);
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})
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;; Attempt to always use XOR for zeroing registers (including FP modes).
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