rs6000.md (div<mode>3): Fix comment.
2014-09-21 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.md (div<mode>3): Fix comment. Use a different insn for divides by integer powers of two. (div<mode>3_sra, *div<mode>3_sra_dot, *div<mode>3_sra_dot2): New. (mod<mode>3): Fix formatting. (three anonymous define_insn and two define_split): Delete. From-SVN: r215437
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@ -1,3 +1,11 @@
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (div<mode>3): Fix comment. Use a different
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insn for divides by integer powers of two.
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(div<mode>3_sra, *div<mode>3_sra_dot, *div<mode>3_sra_dot2): New.
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(mod<mode>3): Fix formatting.
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(three anonymous define_insn and two define_split): Delete.
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (ashr<mode>3, *ashr<mode>3, *ashrsi3_64,
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@ -2488,7 +2488,7 @@
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(set_attr "size" "<bits>")])
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;; For powers of two we can do srai/aze for divide and then adjust for
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;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
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;; modulus. If it isn't a power of two, force operands into register and do
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;; a normal divide.
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(define_expand "div<mode>3"
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@ -2497,10 +2497,15 @@
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(match_operand:GPR 2 "reg_or_cint_operand" "")))]
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""
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{
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if (GET_CODE (operands[2]) != CONST_INT
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|| INTVAL (operands[2]) <= 0
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|| exact_log2 (INTVAL (operands[2])) < 0)
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operands[2] = force_reg (<MODE>mode, operands[2]);
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if (CONST_INT_P (operands[2])
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&& INTVAL (operands[2]) > 0
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&& exact_log2 (INTVAL (operands[2])) >= 0)
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{
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emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
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DONE;
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}
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operands[2] = force_reg (<MODE>mode, operands[2]);
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})
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(define_insn "*div<mode>3"
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@ -2512,12 +2517,71 @@
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[(set_attr "type" "div")
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(set_attr "size" "<bits>")])
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(define_insn "div<mode>3_sra"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "exact_log2_cint_operand" "N")))
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(clobber (reg:GPR CA_REGNO))]
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""
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"sra<wd>i %0,%1,%p2\;addze %0,%0"
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[(set_attr "type" "two")
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(set_attr "length" "8")])
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(define_insn_and_split "*div<mode>3_sra_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))
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(clobber (reg:GPR CA_REGNO))]
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"<MODE>mode == Pmode"
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"@
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sra<wd>i %0,%1,%p2\;addze. %0,%0
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(parallel [(set (match_dup 0)
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(div:GPR (match_dup 1)
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(match_dup 2)))
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(clobber (reg:GPR CA_REGNO))])
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "two")
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(set_attr "length" "8,12")
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(set_attr "cell_micro" "not")])
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(define_insn_and_split "*div<mode>3_sra_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(div:GPR (match_dup 1)
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(match_dup 2)))
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(clobber (reg:GPR CA_REGNO))]
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"<MODE>mode == Pmode"
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"@
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sra<wd>i %0,%1,%p2\;addze. %0,%0
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(parallel [(set (match_dup 0)
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(div:GPR (match_dup 1)
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(match_dup 2)))
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(clobber (reg:GPR CA_REGNO))])
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "two")
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(set_attr "length" "8,12")
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(set_attr "cell_micro" "not")])
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(define_expand "mod<mode>3"
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[(use (match_operand:GPR 0 "gpc_reg_operand" ""))
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(use (match_operand:GPR 1 "gpc_reg_operand" ""))
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(use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
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""
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"
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{
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int i;
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rtx temp1;
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@ -2535,76 +2599,7 @@
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emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
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emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
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DONE;
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}")
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(define_insn ""
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
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""
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"sra<wd>i %0,%1,%p2\;addze %0,%0"
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[(set_attr "type" "two")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "exact_log2_cint_operand" "N,N"))
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(const_int 0)))
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(clobber (match_scratch:P 3 "=r,r"))]
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""
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"@
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sra<wd>i %3,%1,%p2\;addze. %3,%3
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12")
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(set_attr "cell_micro" "not")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "exact_log2_cint_operand"
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""))
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(const_int 0)))
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(clobber (match_scratch:GPR 3 ""))]
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"reload_completed"
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[(set (match_dup 3)
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(div:<MODE> (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "exact_log2_cint_operand" "N,N"))
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(const_int 0)))
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
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(div:P (match_dup 1) (match_dup 2)))]
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""
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"@
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sra<wd>i %0,%1,%p2\;addze. %0,%0
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12")
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(set_attr "cell_micro" "not")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "exact_log2_cint_operand"
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""))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(div:GPR (match_dup 1) (match_dup 2)))]
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"reload_completed"
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[(set (match_dup 0)
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(div:<MODE> (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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})
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;; Logical instructions
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;; The logical instructions are mostly combined by using match_operator,
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