rs6000.h (HARD_REGNO_MODE_OK): Allow arbitrary modes in CTR/LR/MQ.
* config/rs6000/rs6000.h (HARD_REGNO_MODE_OK): Allow arbitrary modes in CTR/LR/MQ. * config/rs6000/rs6000.md (movcc_internal1): Support CCmode moves to/from CTR/LR/MQ. (movsf_hardfloat): Support SFmode moves to/from CTR/LR/MQ. (movsf_softfloat): Likewise. From-SVN: r58267
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@ -1,3 +1,12 @@
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2002-10-17 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000.h (HARD_REGNO_MODE_OK): Allow arbitrary modes
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in CTR/LR/MQ.
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* config/rs6000/rs6000.md (movcc_internal1): Support CCmode moves
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to/from CTR/LR/MQ.
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(movsf_hardfloat): Support SFmode moves to/from CTR/LR/MQ.
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(movsf_softfloat): Likewise.
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2002-10-17 Janis Johnson <janis187@us.ibm.com>
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* Makefile.in (site.exp): Add ALT_CXX_UNDER_TEST and COMPAT_OPTIONS.
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@ -903,8 +903,7 @@ extern int rs6000_default_long_calls;
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: SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
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: CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
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: XER_REGNO_P (REGNO) ? (MODE) == PSImode \
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: ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
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: ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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: 1)
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/* Value is 1 if it is a good idea to tie two pseudo registers
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@ -8349,8 +8349,8 @@
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"")
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(define_insn "*movcc_internal1"
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[(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
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(match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
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[(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,cl,q,r,r,m")
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(match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,r,r,h,m,r"))]
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"register_operand (operands[0], CCmode)
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|| register_operand (operands[1], CCmode)"
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"@
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@ -8360,10 +8360,13 @@
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mfcr %0
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mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
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mr %0,%1
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mt%0 %1
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mt%0 %1
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mf%1 %0
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{l%U1%X1|lwz%U1%X1} %0,%1
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{st%U0%U1|stw%U0%U1} %1,%0"
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[(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,load,store")
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(set_attr "length" "*,*,12,*,8,*,*,*")])
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[(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,*,mtjmpr,*,load,store")
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(set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
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;; For floating-point, we normally deal with the floating-point registers
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;; unless -msoft-float is used. The sole exception is that parameter passing
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@ -8402,8 +8405,8 @@
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}")
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(define_insn "*movsf_hardfloat"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
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(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
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[(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
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(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
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"(gpc_reg_operand (operands[0], SFmode)
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|| gpc_reg_operand (operands[1], SFmode))
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&& (TARGET_HARD_FLOAT && TARGET_FPRS)"
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@ -8414,19 +8417,25 @@
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fmr %0,%1
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lfs%U1%X1 %0,%1
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stfs%U0%X0 %1,%0
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mt%0 %1
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mt%0 %1
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mf%1 %0
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#
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#"
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[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,8")])
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[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
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(define_insn "*movsf_softfloat"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
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(match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
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[(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r")
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(match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))]
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"(gpc_reg_operand (operands[0], SFmode)
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|| gpc_reg_operand (operands[1], SFmode))
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&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
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"@
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mr %0,%1
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mt%0 %1
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mt%0 %1
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mf%1 %0
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{l%U1%X1|lwz%U1%X1} %0,%1
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{st%U0%X0|stw%U0%X0} %1,%0
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{lil|li} %0,%1
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@ -8434,8 +8443,8 @@
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{cal|la} %0,%a1
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#
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#"
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[(set_attr "type" "*,load,store,*,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,8")])
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[(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
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(define_expand "movdf"
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