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AVX-512. 66/n. Extend vpalignr insn patterns. 

gcc/
	* config/i386/sse.md
	(define_mode_iterator SSESCALARMODE): Add V4TI mode.
	(define_insn "<ssse3_avx2>_palignr<mode>_mask"): New.
	(define_insn "<ssse3_avx2>_palignr<mode>"): Add EVEX version.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216183
This commit is contained in:
Alexander Ivchenko 2014-10-14 08:35:12 +00:00 committed by Kirill Yukhin
parent 2ac7a566e8
commit b99ba39a84
2 changed files with 40 additions and 4 deletions
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14
gcc/ChangeLog
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@ -1,3 +1,17 @@
2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md
(define_mode_iterator SSESCALARMODE): Add V4TI mode.
(define_insn "<ssse3_avx2>_palignr<mode>_mask"): New.
(define_insn "<ssse3_avx2>_palignr<mode>"): Add EVEX version.
2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>

30
gcc/config/i386/sse.md
View File

@ -350,7 +350,7 @@
;; ??? This should probably be dropped in favor of VIMAX_AVX2.
(define_mode_iterator SSESCALARMODE
[(V2TI "TARGET_AVX2") TI])
[(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") TI])
(define_mode_iterator VI12_AVX2
[(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI
@ -13455,11 +13455,33 @@
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "<ssse3_avx2>_palignr<mode>_mask"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=v")
(vec_merge:VI1_AVX2
(unspec:VI1_AVX2
[(match_operand:VI1_AVX2 1 "register_operand" "v")
(match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
UNSPEC_PALIGNR)
(match_operand:VI1_AVX2 4 "vector_move_operand" "0C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
{
operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
return "vpalignr\t{%3, %2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2, %3}";
}
[(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<ssse3_avx2>_palignr<mode>"
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x")
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v")
(unspec:SSESCALARMODE
[(match_operand:SSESCALARMODE 1 "register_operand" "0,x")
(match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm")
[(match_operand:SSESCALARMODE 1 "register_operand" "0,v")
(match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,vm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"