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[RS6000] Remove vec_shl and (hopefully) fix vec_shr

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* config/rs6000/vector.md (vec_shl_<mode>): Remove.
	(vec_shr_<mode>): Reverse shift if BYTES_BIG_ENDIAN.

From-SVN: r217552
This commit is contained in:
Alan Lawrence 2014-11-14 11:18:21 +00:00 committed by Alan Lawrence
parent ebaea9baf5
commit ba067536a7
2 changed files with 9 additions and 44 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2014-11-14 Alan Lawrence <alan.lawrence@arm.com>
* config/rs6000/vector.md (vec_shl_<mode>): Remove.
(vec_shr_<mode>): Reverse shift if BYTES_BIG_ENDIAN.
2014-11-14 Alan Lawrence <alan.lawrence@arm.com>
* optabs.c (shift_amt_for_vec_perm_mask): Remove code conditional on

48
gcc/config/rs6000/vector.md
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@ -960,53 +960,11 @@
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
;; Vector shift left in bits. Currently supported ony for shift
;; amounts that can be expressed as byte shifts (divisible by 8).
;; General shift amounts can be supported using vslo + vsl. We're
;; not expecting to see these yet (the vectorizer currently
;; generates only shifts divisible by byte_size).
(define_expand "vec_shl_<mode>"
[(match_operand:VEC_L 0 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")
(match_operand:QI 2 "reg_or_short_operand" "")]
"TARGET_ALTIVEC"
"
{
rtx bitshift = operands[2];
rtx shift;
rtx insn;
HOST_WIDE_INT bitshift_val;
HOST_WIDE_INT byteshift_val;
if (! CONSTANT_P (bitshift))
FAIL;
bitshift_val = INTVAL (bitshift);
if (bitshift_val & 0x7)
FAIL;
byteshift_val = bitshift_val >> 3;
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
{
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
shift);
}
else
{
shift = gen_rtx_CONST_INT (QImode, byteshift_val);
insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
shift);
}
emit_insn (insn);
DONE;
}")
;; Vector shift right in bits. Currently supported ony for shift
;; amounts that can be expressed as byte shifts (divisible by 8).
;; General shift amounts can be supported using vsro + vsr. We're
;; not expecting to see these yet (the vectorizer currently
;; generates only shifts divisible by byte_size).
;; generates only shifts by a whole number of vector elements).
(define_expand "vec_shr_<mode>"
[(match_operand:VEC_L 0 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")
@ -1025,7 +983,9 @@
bitshift_val = INTVAL (bitshift);
if (bitshift_val & 0x7)
FAIL;
byteshift_val = 16 - (bitshift_val >> 3);
byteshift_val = (bitshift_val >> 3);
if (!BYTES_BIG_ENDIAN)
byteshift_val = 16 - byteshift_val;
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
{
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);