re PR tree-optimization/35252 (No vectorization for complex arrays)
2008-08-02 Richard Guenther <rguenther@suse.de> PR target/35252 * config/i386/sse.md (SSEMODE4S, SSEMODE2D): New mode iterators. (ssedoublesizemode): New mode attribute. (sse_shufps): Call gen_sse_shufps_v4sf. (sse_shufps_1): Macroize. (sse2_shufpd): Call gen_Sse_shufpd_v2df. (sse2_shufpd_1): Macroize. (vec_extract_odd, vec_extract_even): New expanders. (vec_interleave_highv4sf, vec_interleave_lowv4sf, vec_interleave_highv2df, vec_interleave_lowv2df): Likewise. * i386.c (ix86_expand_vector_init_one_nonzero): Call gen_sse_shufps_v4sf instead of gen_sse_shufps_1. (ix86_expand_vector_set): Likewise. (ix86_expand_reduc_v4sf): Likewise. * lib/target-supports.exp (vect_extract_even_odd_wide) Add. (vect_strided_wide): Likewise. * gcc.dg/vect/fast-math-pr35982.c: Enable for vect_extract_even_odd_wide. * gcc.dg/vect/fast-math-vect-complex-3.c: Likewise. * gcc.dg/vect/vect-1.c: Likewise. * gcc.dg/vect/vect-107.c: Likewise. * gcc.dg/vect/vect-98.c: Likewise. * gcc.dg/vect/vect-strided-float.c: Likewise. * gcc.dg/vect/slp-11.c: Enable for vect_strided_wide. * gcc.dg/vect/slp-12a.c: Likewise. * gcc.dg/vect/slp-12b.c: Likewise. * gcc.dg/vect/slp-19.c: Likewise. * gcc.dg/vect/slp-23.c: Likewise. * gcc.dg/vect/slp-5.c: Likewise. From-SVN: r138553
This commit is contained in:
Richard Guenther
Richard Biener
parent
d2143736bb
commit
ba63dfb918
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@ -1,3 +1,20 @@
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2008-08-02 Richard Guenther <rguenther@suse.de>
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PR target/35252
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* config/i386/sse.md (SSEMODE4S, SSEMODE2D): New mode iterators.
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(ssedoublesizemode): New mode attribute.
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(sse_shufps): Call gen_sse_shufps_v4sf.
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(sse_shufps_1): Macroize.
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(sse2_shufpd): Call gen_Sse_shufpd_v2df.
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(sse2_shufpd_1): Macroize.
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(vec_extract_odd, vec_extract_even): New expanders.
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(vec_interleave_highv4sf, vec_interleave_lowv4sf,
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vec_interleave_highv2df, vec_interleave_lowv2df): Likewise.
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* i386.c (ix86_expand_vector_init_one_nonzero): Call
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gen_sse_shufps_v4sf instead of gen_sse_shufps_1.
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(ix86_expand_vector_set): Likewise.
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(ix86_expand_reduc_v4sf): Likewise.
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2008-08-01 Doug Kwan <dougkwan@google.com>
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* matrix-reorg.c: Re-enable all code.
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@ -25176,7 +25176,7 @@ ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
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else
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tmp = new_target;
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emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
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emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
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GEN_INT (1),
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GEN_INT (one_var == 1 ? 0 : 1),
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GEN_INT (one_var == 2 ? 0+4 : 1+4),
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@ -25740,7 +25740,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
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/* target = X A B B */
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ix86_expand_vector_set (false, target, val, 0);
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/* target = A X C D */
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emit_insn (gen_sse_shufps_1 (target, target, tmp,
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emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
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GEN_INT (1), GEN_INT (0),
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GEN_INT (2+4), GEN_INT (3+4)));
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return;
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@ -25751,7 +25751,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
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/* tmp = X B C D */
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ix86_expand_vector_set (false, tmp, val, 0);
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/* target = A B X D */
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emit_insn (gen_sse_shufps_1 (target, target, tmp,
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emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
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GEN_INT (0), GEN_INT (1),
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GEN_INT (0+4), GEN_INT (3+4)));
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return;
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@ -25762,7 +25762,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
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/* tmp = X B C D */
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ix86_expand_vector_set (false, tmp, val, 0);
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/* target = A B X D */
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emit_insn (gen_sse_shufps_1 (target, target, tmp,
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emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
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GEN_INT (0), GEN_INT (1),
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GEN_INT (2+4), GEN_INT (0+4)));
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return;
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@ -25883,7 +25883,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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case 1:
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case 3:
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tmp = gen_reg_rtx (mode);
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emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
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emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
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GEN_INT (elt), GEN_INT (elt),
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GEN_INT (elt+4), GEN_INT (elt+4)));
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break;
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@ -26000,7 +26000,7 @@ ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
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emit_insn (gen_sse_movhlps (tmp1, in, in));
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emit_insn (fn (tmp2, tmp1, in));
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emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
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emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
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GEN_INT (1), GEN_INT (1),
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GEN_INT (1+4), GEN_INT (1+4)));
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emit_insn (fn (dest, tmp2, tmp3));
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@ -36,6 +36,10 @@
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(define_mode_iterator SSEMODEF4 [SF DF V4SF V2DF])
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(define_mode_iterator SSEMODEF2P [V4SF V2DF])
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;; Int-float size matches
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(define_mode_iterator SSEMODE4S [V4SF V4SI])
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(define_mode_iterator SSEMODE2D [V2DF V2DI])
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;; Mapping from float mode to required SSE level
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(define_mode_attr sse [(SF "sse") (DF "sse2") (V4SF "sse") (V2DF "sse2")])
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@ -57,6 +61,10 @@
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(V16QI "QI") (V8HI "HI")
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(V4SI "SI") (V2DI "DI")])
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;; Mapping of vector modes to a vector mode of double size
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(define_mode_attr ssedoublesizemode [(V2DF "V4DF") (V2DI "V4DI")
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(V4SF "V8SF") (V4SI "V8SI")])
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;; Number of scalar elements in each vector type
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(define_mode_attr ssescalarnum [(V4SF "4") (V2DF "2")
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(V16QI "16") (V8HI "8")
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@ -2129,7 +2137,7 @@
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"TARGET_SSE"
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{
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int mask = INTVAL (operands[3]);
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emit_insn (gen_sse_shufps_1 (operands[0], operands[1], operands[2],
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emit_insn (gen_sse_shufps_v4sf (operands[0], operands[1], operands[2],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT (((mask >> 4) & 3) + 4),
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@ -2137,12 +2145,12 @@
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DONE;
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})
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(define_insn "sse_shufps_1"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(vec_select:V4SF
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(vec_concat:V8SF
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(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm"))
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(define_insn "sse_shufps_<mode>"
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[(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
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(vec_select:SSEMODE4S
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE4S 1 "register_operand" "0")
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(match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
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(parallel [(match_operand 3 "const_0_to_3_operand" "")
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(match_operand 4 "const_0_to_3_operand" "")
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(match_operand 5 "const_4_to_7_operand" "")
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@ -2540,18 +2548,62 @@
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"TARGET_SSE2"
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{
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int mask = INTVAL (operands[3]);
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emit_insn (gen_sse2_shufpd_1 (operands[0], operands[1], operands[2],
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emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
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GEN_INT (mask & 1),
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GEN_INT (mask & 2 ? 3 : 2)));
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DONE;
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})
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(define_insn "sse2_shufpd_1"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(vec_select:V2DF
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(vec_concat:V4DF
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(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm"))
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(define_expand "vec_extract_even<mode>"
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[(set (match_operand:SSEMODE4S 0 "register_operand" "")
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(vec_select:SSEMODE4S
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE4S 1 "register_operand" "")
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(match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
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(parallel [(const_int 0)
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(const_int 2)
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(const_int 4)
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(const_int 6)])))]
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"TARGET_SSE")
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(define_expand "vec_extract_odd<mode>"
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[(set (match_operand:SSEMODE4S 0 "register_operand" "")
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(vec_select:SSEMODE4S
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE4S 1 "register_operand" "")
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(match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
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(parallel [(const_int 1)
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(const_int 3)
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(const_int 5)
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(const_int 7)])))]
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"TARGET_SSE")
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(define_expand "vec_extract_even<mode>"
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[(set (match_operand:SSEMODE2D 0 "register_operand" "")
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(vec_select:SSEMODE2D
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE2D 1 "register_operand" "")
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(match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
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(parallel [(const_int 0)
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(const_int 2)])))]
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"TARGET_SSE2")
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(define_expand "vec_extract_odd<mode>"
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[(set (match_operand:SSEMODE2D 0 "register_operand" "")
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(vec_select:SSEMODE2D
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE2D 1 "register_operand" "")
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(match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
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(parallel [(const_int 1)
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(const_int 3)])))]
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"TARGET_SSE2")
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(define_insn "sse2_shufpd_<mode>"
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[(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
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(vec_select:SSEMODE2D
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(vec_concat:<ssedoublesizemode>
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(match_operand:SSEMODE2D 1 "register_operand" "0")
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(match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
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(parallel [(match_operand 3 "const_0_to_1_operand" "")
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(match_operand 4 "const_2_to_3_operand" "")])))]
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"TARGET_SSE2"
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@ -4195,6 +4247,46 @@
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DONE;
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})
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(define_expand "vec_interleave_highv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "")
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(vec_select:V4SF
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(vec_concat:V8SF
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(match_operand:V4SF 1 "register_operand" "")
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(match_operand:V4SF 2 "nonimmediate_operand" ""))
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(parallel [(const_int 2) (const_int 6)
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(const_int 3) (const_int 7)])))]
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"TARGET_SSE")
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(define_expand "vec_interleave_lowv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "")
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(vec_select:V4SF
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(vec_concat:V8SF
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(match_operand:V4SF 1 "register_operand" "")
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(match_operand:V4SF 2 "nonimmediate_operand" ""))
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(parallel [(const_int 0) (const_int 4)
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(const_int 1) (const_int 5)])))]
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"TARGET_SSE")
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(define_expand "vec_interleave_highv2df"
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[(set (match_operand:V2DF 0 "register_operand" "")
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(vec_select:V2DF
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(vec_concat:V4DF
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(match_operand:V2DF 1 "register_operand" "")
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(match_operand:V2DF 2 "nonimmediate_operand" ""))
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(parallel [(const_int 1)
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(const_int 3)])))]
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"TARGET_SSE2")
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(define_expand "vec_interleave_lowv2df"
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[(set (match_operand:V2DF 0 "register_operand" "")
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(vec_select:V2DF
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(vec_concat:V4DF
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(match_operand:V2DF 1 "register_operand" "")
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(match_operand:V2DF 2 "nonimmediate_operand" ""))
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(parallel [(const_int 0)
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(const_int 2)])))]
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"TARGET_SSE2")
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(define_insn "sse2_packsswb"
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[(set (match_operand:V16QI 0 "register_operand" "=x")
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(vec_concat:V16QI
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@ -1,3 +1,22 @@
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2008-08-02 Richard Guenther <rguenther@suse.de>
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PR target/35252
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* lib/target-supports.exp (vect_extract_even_odd_wide) Add.
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(vect_strided_wide): Likewise.
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* gcc.dg/vect/fast-math-pr35982.c: Enable for
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vect_extract_even_odd_wide.
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* gcc.dg/vect/fast-math-vect-complex-3.c: Likewise.
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* gcc.dg/vect/vect-1.c: Likewise.
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* gcc.dg/vect/vect-107.c: Likewise.
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* gcc.dg/vect/vect-98.c: Likewise.
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* gcc.dg/vect/vect-strided-float.c: Likewise.
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* gcc.dg/vect/slp-11.c: Enable for vect_strided_wide.
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* gcc.dg/vect/slp-12a.c: Likewise.
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* gcc.dg/vect/slp-12b.c: Likewise.
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* gcc.dg/vect/slp-19.c: Likewise.
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* gcc.dg/vect/slp-23.c: Likewise.
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* gcc.dg/vect/slp-5.c: Likewise.
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2008-08-02 Eric Botcazou <ebotcazou@adacore.com>
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* gnat.dg/boolean_expr2.adb: New test.
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@ -19,7 +19,7 @@ float method2_int16 (struct mem *mem)
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return avg;
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}
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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@ -57,5 +57,5 @@ main (void)
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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@ -106,8 +106,8 @@ int main (void)
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { vect_strided && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! { vect_int_mult && vect_strided } } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { vect_strided_wide && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! { vect_int_mult && vect_strided_wide } } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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@ -95,11 +95,11 @@ int main (void)
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { vect_strided && vect_int_mult} } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { {! {vect_strided}} && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult} } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided}} && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { ! vect_int_mult } } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -43,9 +43,9 @@ int main (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { vect_strided && vect_int_mult } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided}}} } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { vect_strided && vect_int_mult } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided}}} } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -147,9 +147,9 @@ int main (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target vect_strided } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided } } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target vect_strided } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! { vect_strided } } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target vect_strided_wide } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide } } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target vect_strided_wide } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! { vect_strided_wide } } } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -106,8 +106,8 @@ int main (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided } && {! { vect_no_align} } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided || vect_no_align} } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided_wide } && {! { vect_no_align} } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide || vect_no_align} } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail vect_no_align } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -121,8 +121,8 @@ int main (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { vect_strided } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! { vect_strided } } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { vect_strided_wide } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! { vect_strided_wide } } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -86,6 +86,6 @@ foo (int n)
|
|||
fbar (a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target vect_extract_even_odd } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
|
|
|||
|
|
@ -39,6 +39,6 @@ int main (void)
|
|||
return main1 ();
|
||||
}
|
||||
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,6 @@ int main (void)
|
|||
}
|
||||
|
||||
/* Needs interleaving support. */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ int main (void)
|
|||
}
|
||||
|
||||
/* Needs interleaving support. */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
|
||||
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
|
||||
/* { dg-final { cleanup-tree-dump "vect" } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -2078,6 +2078,27 @@ proc check_effective_target_vect_extract_even_odd { } {
|
|||
return $et_vect_extract_even_odd_saved
|
||||
}
|
||||
|
||||
# Return 1 if the target supports vector even/odd elements extraction of
|
||||
# vectors with SImode elements or larger, 0 otherwise.
|
||||
|
||||
proc check_effective_target_vect_extract_even_odd_wide { } {
|
||||
global et_vect_extract_even_odd_wide_saved
|
||||
|
||||
if [info exists et_vect_extract_even_odd_wide_saved] {
|
||||
verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
|
||||
} else {
|
||||
set et_vect_extract_even_odd_wide_saved 0
|
||||
if { [istarget powerpc*-*-*]
|
||||
|| [istarget i?86-*-*]
|
||||
|| [istarget x86_64-*-*] } {
|
||||
set et_vect_extract_even_odd_wide_saved 1
|
||||
}
|
||||
}
|
||||
|
||||
verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
|
||||
return $et_vect_extract_even_odd_wide_saved
|
||||
}
|
||||
|
||||
# Return 1 if the target supports vector interleaving, 0 otherwise.
|
||||
|
||||
proc check_effective_target_vect_interleave { } {
|
||||
|
|
@ -2116,6 +2137,25 @@ proc check_effective_target_vect_strided { } {
|
|||
return $et_vect_strided_saved
|
||||
}
|
||||
|
||||
# Return 1 if the target supports vector interleaving and extract even/odd
|
||||
# for wide element types, 0 otherwise.
|
||||
proc check_effective_target_vect_strided_wide { } {
|
||||
global et_vect_strided_wide_saved
|
||||
|
||||
if [info exists et_vect_strided_wide_saved] {
|
||||
verbose "check_effective_target_vect_strided_wide: using cached result" 2
|
||||
} else {
|
||||
set et_vect_strided_wide_saved 0
|
||||
if { [check_effective_target_vect_interleave]
|
||||
&& [check_effective_target_vect_extract_even_odd_wide] } {
|
||||
set et_vect_strided_wide_saved 1
|
||||
}
|
||||
}
|
||||
|
||||
verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
|
||||
return $et_vect_strided_wide_saved
|
||||
}
|
||||
|
||||
# Return 1 if the target supports section-anchors
|
||||
|
||||
proc check_effective_target_section_anchors { } {
|
||||
|
|
|
|||
Loading…
Reference in New Issue