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[AArch64, PATCH] Improve Neon store of zero

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Committed on behalf of Jackson Woodruff.

---
gcc/

	* config/aarch64/constraints.md (Umq): New constraint.
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>):
	Change to use Umq.
	(mov<mode>): Update condition.

gcc/testsuite/

	* gcc.target/aarch64/simd/vect_str_zero.c: Update testcase.

From-SVN: r252387
This commit is contained in:
Jackson Woodruff 2017-09-13 16:49:42 +00:00 committed by James Greenhalgh
parent 267bbb6fd1
commit bb5d97112a
5 changed files with 35 additions and 7 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2017-09-13 Jackson Woodruff <jackson.woodruff@arm.com>
* config/aarch64/constraints.md (Umq): New constraint.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>):
Change to use Umq.
(mov<mode>): Update condition.
2017-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gimple-ssa-store-merging.c (sort_by_bitpos): Compare store order

17
gcc/config/aarch64/aarch64-simd.md
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@ -23,10 +23,17 @@
(match_operand:VALL_F16 1 "general_operand" ""))]
"TARGET_SIMD"
"
if (GET_CODE (operands[0]) == MEM
&& !(aarch64_simd_imm_zero (operands[1], <MODE>mode)
&& aarch64_legitimate_address_p (<MODE>mode, operands[0],
PARALLEL, 1)))
/* Force the operand into a register if it is not an
immediate whose use can be replaced with xzr.
If the mode is 16 bytes wide, then we will be doing
a stp in DI mode, so we check the validity of that.
If the mode is 8 bytes wide, then we will do doing a
normal str, so the check need not apply. */
if (GET_CODE (operands[0]) == MEM
&& !(aarch64_simd_imm_zero (operands[1], <MODE>mode)
&& ((GET_MODE_SIZE (<MODE>mode) == 16
&& aarch64_mem_pair_operand (operands[0], DImode))
|| GET_MODE_SIZE (<MODE>mode) == 8)))
operands[1] = force_reg (<MODE>mode, operands[1]);
"
)
@ -126,7 +133,7 @@
(define_insn "*aarch64_simd_mov<mode>"
[(set (match_operand:VQ 0 "nonimmediate_operand"
"=w, Ump, m, w, ?r, ?w, ?r, w")
"=w, Umq, m, w, ?r, ?w, ?r, w")
(match_operand:VQ 1 "general_operand"
"m, Dz, w, w, w, r, r, Dn"))]
"TARGET_SIMD

8
gcc/config/aarch64/constraints.md
View File

@ -156,6 +156,14 @@
(and (match_code "mem")
(match_test "REG_P (XEXP (op, 0))")))
(define_memory_constraint "Umq"
"@internal
A memory address which uses a base register with an offset small enough for
a load/store pair operation in DI mode."
(and (match_code "mem")
(match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0),
PARALLEL, false)")))
(define_memory_constraint "Ump"
"@internal
A memory address suitable for a load/store pair operation."

4
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2017-09-13 Jackson Woodruff <jackson.woodruff@arm.com>
* gcc.target/aarch64/simd/vect_str_zero.c: Update testcase.
2017-09-13 Marek Polacek <polacek@redhat.com>
PR c/82167

6
gcc/testsuite/gcc.target/aarch64/simd/vect_str_zero.c
View File

@ -7,7 +7,7 @@ void
f (uint32x4_t *p)
{
uint32x4_t x = { 0, 0, 0, 0};
p[1] = x;
p[4] = x;
/* { dg-final { scan-assembler "stp\txzr, xzr," } } */
}
@ -16,7 +16,9 @@ void
g (float32x2_t *p)
{
float32x2_t x = {0.0, 0.0};
p[0] = x;
p[400] = x;
/* { dg-final { scan-assembler "str\txzr, " } } */
}
/* { dg-final { scan-assembler-not "add\tx\[0-9\]\+, x0, \[0-9\]+" } } */