rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs. * config/bfin/bfin.c: Include "timevar.h". (bfin_flag_schedule_insns2, splitting_for_sched, bfin_flag_var_tracking): New variables. (print_operand): Handle '%!'. (override_options): Disable normal sched2 pass, instead set bfin_flag_schedule_insns2 for reorg to handle it. (output_file_start): Likewise for var-tracking. (bfin_optimize_loop): Take some care not to stumble over SEQUENCEs. (gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p): New functions. (bfin_reorg): Do second scheduling pass here, and call bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead of examining insns directly. If bfin_flag_var_tracking, call var-tracking pass when done with everything else. * config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid. * config/bfin/bfin.md (UNSPEC_32BIT): New constant. (movsi_insn32): New pattern, with two new splits to create it before the final scheduling pass. (neghi2): Not a dsp32 insn, rather alu0. (movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn, movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2, extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2, mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2, ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2, movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi, ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3, addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3, flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi, flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3, flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts, flag_macv2hi_parts_acconly, flag_macinitv2hi_parts, flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store variants instead of ';'. (ror_one, rol_one): Likewise. Make them dsp32 insns. (ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants. (align8, align16, align24): Now named patterns; also using '%!'. (mnop): New insn. From-SVN: r119534
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
9fc4da9d86
commit
bbbc206e9f
@ -1,3 +1,49 @@
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2006-12-04 Bernd Schmidt <bernd.schmidt@analog.com>
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* rtlanal.c (note_uses): Deal with SEQUENCEs.
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* config/bfin/bfin.c: Include "timevar.h".
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(bfin_flag_schedule_insns2, splitting_for_sched,
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bfin_flag_var_tracking): New variables.
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(print_operand): Handle '%!'.
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(override_options): Disable normal sched2 pass, instead set
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bfin_flag_schedule_insns2 for reorg to handle it.
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(output_file_start): Likewise for var-tracking.
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(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
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(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
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New functions.
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(bfin_reorg): Do second scheduling pass here, and call
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bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
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of examining insns directly. If bfin_flag_var_tracking, call
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var-tracking pass when done with everything else.
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* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
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* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
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(movsi_insn32): New pattern, with two new splits to create it
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before the final scheduling pass.
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(neghi2): Not a dsp32 insn, rather alu0.
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(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
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movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
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extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
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mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
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ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
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movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
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movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
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ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
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addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
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subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
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addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
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flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
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flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
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flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
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flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
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flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
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mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
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lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
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variants instead of ';'.
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(ror_one, rol_one): Likewise. Make them dsp32 insns.
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(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
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(align8, align16, align24): Now named patterns; also using '%!'.
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(mnop): New insn.
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2006-12-05 Kazu Hirata <kazu@codesourcery.com>
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* config/i386/darwin.h, config/spu/spu.c, tree-ssa-live.c,
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@ -52,6 +52,7 @@
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#include "tm-preds.h"
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#include "gt-bfin.h"
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#include "basic-block.h"
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#include "timevar.h"
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/* A C structure for machine-specific, per-function data.
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This is added to the cfun structure. */
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@ -82,6 +83,16 @@ static int arg_regs[] = FUNCTION_ARG_REGISTERS;
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/* Nonzero if -mshared-library-id was given. */
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static int bfin_lib_id_given;
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/* Nonzero if -fschedule-insns2 was given. We override it and
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call the scheduler ourselves during reorg. */
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static int bfin_flag_schedule_insns2;
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/* Determines whether we run variable tracking in machine dependent
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reorganization. */
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static int bfin_flag_var_tracking;
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int splitting_for_sched;
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static void
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bfin_globalize_label (FILE *stream, const char *name)
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{
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@ -97,6 +108,13 @@ output_file_start (void)
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FILE *file = asm_out_file;
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int i;
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/* Variable tracking should be run after all optimizations which change order
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of insns. It also needs a valid CFG. This can't be done in
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ia64_override_options, because flag_var_tracking is finalized after
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that. */
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bfin_flag_var_tracking = flag_var_tracking;
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flag_var_tracking = 0;
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fprintf (file, ".file \"%s\";\n", input_filename);
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for (i = 0; arg_regs[i] >= 0; i++)
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@ -1161,7 +1179,18 @@ print_address_operand (FILE *file, rtx x)
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void
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print_operand (FILE *file, rtx x, char code)
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{
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enum machine_mode mode = GET_MODE (x);
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enum machine_mode mode;
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if (code == '!')
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{
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if (GET_MODE (current_output_insn) == SImode)
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fprintf (file, " ||");
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else
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fprintf (file, ";");
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return;
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}
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mode = GET_MODE (x);
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switch (code)
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{
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@ -2079,6 +2108,11 @@ override_options (void)
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flag_schedule_insns = 0;
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/* Passes after sched2 can break the helpful TImode annotations that
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haifa-sched puts on every insn. Just do scheduling in reorg. */
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bfin_flag_schedule_insns2 = flag_schedule_insns_after_reload;
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flag_schedule_insns_after_reload = 0;
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init_machine_status = bfin_init_machine_status;
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}
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@ -3243,7 +3277,8 @@ bfin_optimize_loop (loop_info loop)
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}
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}
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else if (CALL_P (last_insn)
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|| get_attr_type (last_insn) == TYPE_SYNC
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|| (GET_CODE (PATTERN (last_insn)) != SEQUENCE
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&& get_attr_type (last_insn) == TYPE_SYNC)
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|| recog_memoized (last_insn) == CODE_FOR_return_internal)
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{
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if (dump_file)
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@ -3254,7 +3289,8 @@ bfin_optimize_loop (loop_info loop)
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if (GET_CODE (PATTERN (last_insn)) == ASM_INPUT
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|| asm_noperands (PATTERN (last_insn)) >= 0
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|| get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI)
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|| (GET_CODE (PATTERN (last_insn)) != SEQUENCE
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&& get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI))
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{
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nop_insn = emit_insn_after (gen_nop (), last_insn);
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last_insn = nop_insn;
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@ -3602,9 +3638,184 @@ bfin_reorg_loops (FILE *dump_file)
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if (dump_file)
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print_rtl (dump_file, get_insns ());
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FOR_EACH_BB (bb)
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bb->aux = NULL;
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}
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/* Possibly generate a SEQUENCE out of three insns found in SLOT.
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Returns true if we modified the insn chain, false otherwise. */
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static bool
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gen_one_bundle (rtx slot[3])
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{
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rtx bundle;
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gcc_assert (slot[1] != NULL_RTX);
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/* Verify that we really can do the multi-issue. */
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if (slot[0])
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{
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rtx t = NEXT_INSN (slot[0]);
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while (t != slot[1])
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{
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if (GET_CODE (t) != NOTE
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|| NOTE_LINE_NUMBER (t) != NOTE_INSN_DELETED)
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return false;
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t = NEXT_INSN (t);
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}
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}
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if (slot[2])
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{
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rtx t = NEXT_INSN (slot[1]);
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while (t != slot[2])
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{
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if (GET_CODE (t) != NOTE
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|| NOTE_LINE_NUMBER (t) != NOTE_INSN_DELETED)
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return false;
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t = NEXT_INSN (t);
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}
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}
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if (slot[0] == NULL_RTX)
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slot[0] = emit_insn_before (gen_mnop (), slot[1]);
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if (slot[2] == NULL_RTX)
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slot[2] = emit_insn_after (gen_nop (), slot[1]);
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/* Avoid line number information being printed inside one bundle. */
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if (INSN_LOCATOR (slot[1])
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&& INSN_LOCATOR (slot[1]) != INSN_LOCATOR (slot[0]))
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INSN_LOCATOR (slot[1]) = INSN_LOCATOR (slot[0]);
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if (INSN_LOCATOR (slot[2])
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&& INSN_LOCATOR (slot[2]) != INSN_LOCATOR (slot[0]))
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INSN_LOCATOR (slot[2]) = INSN_LOCATOR (slot[0]);
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/* Terminate them with "|| " instead of ";" in the output. */
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PUT_MODE (slot[0], SImode);
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PUT_MODE (slot[1], SImode);
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/* This is a cheat to avoid emit_insn's special handling of SEQUENCEs.
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Generating a PARALLEL first and changing its code later is the
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easiest way to emit a SEQUENCE insn. */
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bundle = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, slot[0], slot[1], slot[2]));
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emit_insn_before (bundle, slot[0]);
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remove_insn (slot[0]);
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remove_insn (slot[1]);
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remove_insn (slot[2]);
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PUT_CODE (bundle, SEQUENCE);
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return true;
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}
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/* Go through all insns, and use the information generated during scheduling
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to generate SEQUENCEs to represent bundles of instructions issued
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simultaneously. */
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static void
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bfin_gen_bundles (void)
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{
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basic_block bb;
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FOR_EACH_BB (bb)
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{
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rtx insn, next;
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rtx slot[3];
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int n_filled = 0;
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slot[0] = slot[1] = slot[2] = NULL_RTX;
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for (insn = BB_HEAD (bb);; insn = next)
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{
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int at_end;
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if (INSN_P (insn))
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{
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if (get_attr_type (insn) == TYPE_DSP32)
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slot[0] = insn;
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else if (slot[1] == NULL_RTX)
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slot[1] = insn;
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else
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slot[2] = insn;
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n_filled++;
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}
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next = NEXT_INSN (insn);
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while (next && insn != BB_END (bb)
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&& !(INSN_P (next)
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&& GET_CODE (PATTERN (next)) != USE
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&& GET_CODE (PATTERN (next)) != CLOBBER))
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{
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insn = next;
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next = NEXT_INSN (insn);
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}
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/* BB_END can change due to emitting extra NOPs, so check here. */
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at_end = insn == BB_END (bb);
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if (at_end || GET_MODE (next) == TImode)
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{
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if ((n_filled < 2
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|| !gen_one_bundle (slot))
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&& slot[0] != NULL_RTX)
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{
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rtx pat = PATTERN (slot[0]);
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if (GET_CODE (pat) == SET
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&& GET_CODE (SET_SRC (pat)) == UNSPEC
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&& XINT (SET_SRC (pat), 1) == UNSPEC_32BIT)
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{
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SET_SRC (pat) = XVECEXP (SET_SRC (pat), 0, 0);
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INSN_CODE (slot[0]) = -1;
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}
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}
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n_filled = 0;
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slot[0] = slot[1] = slot[2] = NULL_RTX;
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}
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if (at_end)
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break;
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}
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}
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}
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/* Return an insn type for INSN that can be used by the caller for anomaly
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workarounds. This differs from plain get_attr_type in that it handles
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SEQUENCEs. */
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static enum attr_type
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type_for_anomaly (rtx insn)
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{
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rtx pat = PATTERN (insn);
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if (GET_CODE (pat) == SEQUENCE)
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{
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enum attr_type t;
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t = get_attr_type (XVECEXP (pat, 0, 1));
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if (t == TYPE_MCLD)
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return t;
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t = get_attr_type (XVECEXP (pat, 0, 2));
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if (t == TYPE_MCLD)
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return t;
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return TYPE_MCST;
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}
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else
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return get_attr_type (insn);
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}
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/* Return nonzero if INSN contains any loads that may trap. It handles
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SEQUENCEs correctly. */
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static bool
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trapping_loads_p (rtx insn)
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{
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rtx pat = PATTERN (insn);
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if (GET_CODE (pat) == SEQUENCE)
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{
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enum attr_type t;
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t = get_attr_type (XVECEXP (pat, 0, 1));
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if (t == TYPE_MCLD && may_trap_p (SET_SRC (XVECEXP (pat, 0, 1))))
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return true;
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t = get_attr_type (XVECEXP (pat, 0, 2));
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if (t == TYPE_MCLD && may_trap_p (SET_SRC (XVECEXP (pat, 0, 2))))
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return true;
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return false;
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}
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else
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return may_trap_p (SET_SRC (single_set (insn)));
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}
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/* We use the machine specific reorg pass for emitting CSYNC instructions
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after conditional branches as needed.
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@ -3631,6 +3842,27 @@ bfin_reorg (void)
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rtx insn, last_condjump = NULL_RTX;
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int cycles_since_jump = INT_MAX;
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/* We are freeing block_for_insn in the toplev to keep compatibility
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with old MDEP_REORGS that are not CFG based. Recompute it now. */
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compute_bb_for_insn ();
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if (bfin_flag_schedule_insns2)
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{
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splitting_for_sched = 1;
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split_all_insns (0);
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splitting_for_sched = 0;
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update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
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timevar_push (TV_SCHED2);
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schedule_insns ();
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timevar_pop (TV_SCHED2);
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/* Examine the schedule and insert nops as necessary for 64 bit parallel
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instructions. */
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bfin_gen_bundles ();
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}
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/* Doloop optimization */
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if (cfun->machine->has_hardware_loops)
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bfin_reorg_loops (dump_file);
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@ -3666,15 +3898,14 @@ bfin_reorg (void)
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}
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else if (INSN_P (insn))
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{
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enum attr_type type = get_attr_type (insn);
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enum attr_type type = type_for_anomaly (insn);
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int delay_needed = 0;
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if (cycles_since_jump < INT_MAX)
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cycles_since_jump++;
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if (type == TYPE_MCLD && TARGET_SPECLD_ANOMALY)
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{
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rtx pat = single_set (insn);
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if (may_trap_p (SET_SRC (pat)))
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if (trapping_loads_p (insn))
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delay_needed = 3;
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}
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else if (type == TYPE_SYNC && TARGET_CSYNC_ANOMALY)
|
||||
@ -3736,7 +3967,7 @@ bfin_reorg (void)
|
||||
|
||||
if (INSN_P (target))
|
||||
{
|
||||
enum attr_type type = get_attr_type (target);
|
||||
enum attr_type type = type_for_anomaly (target);
|
||||
int delay_needed = 0;
|
||||
if (cycles_since_jump < INT_MAX)
|
||||
cycles_since_jump++;
|
||||
@ -3774,6 +4005,13 @@ bfin_reorg (void)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (bfin_flag_var_tracking)
|
||||
{
|
||||
timevar_push (TV_VAR_TRACKING);
|
||||
variable_tracking_main ();
|
||||
timevar_pop (TV_VAR_TRACKING);
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle interrupt_handler, exception_handler and nmi_handler function
|
||||
|
||||
@ -1233,4 +1233,8 @@ extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
|
||||
|
||||
#define SIZE_ASM_OP "\t.size\t"
|
||||
|
||||
extern int splitting_for_sched;
|
||||
|
||||
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
|
||||
|
||||
#endif /* _BFIN_CONFIG */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1390,6 +1390,11 @@ note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
|
||||
note_uses (&XVECEXP (body, 0, i), fun, data);
|
||||
return;
|
||||
|
||||
case SEQUENCE:
|
||||
for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
|
||||
note_uses (&PATTERN (XVECEXP (body, 0, i)), fun, data);
|
||||
return;
|
||||
|
||||
case USE:
|
||||
(*fun) (&XEXP (body, 0), data);
|
||||
return;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user