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c4x.h (IS_XXX_REG, [...]): Swap behaviour of macros so that they're consistent with their names. 

* config/c4x/c4x.h (IS_XXX_REG, IS_XXX_REGNO): Swap behaviour of
	macros so that they're consistent with their names.
	* config/c4x/c4x.c (IS_XXX_REG, IS_XXX_REGNO): Likewise.
	* config/c4x/c4x.md (IS_XXX_REG, IS_XXX_REGNO): Likewise.

From-SVN: r31221
This commit is contained in:
Michael Hayes 2000-01-04 23:57:40 +00:00 committed by Michael Hayes
parent d79229bd58
commit bc46716b04
4 changed files with 141 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2000-01-05 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x.h (IS_XXX_REG, IS_XXX_REGNO): Swap behaviour of
macros so that they're consistent with their names.
* config/c4x/c4x.c (IS_XXX_REG, IS_XXX_REGNO): Likewise.
* config/c4x/c4x.md (IS_XXX_REG, IS_XXX_REGNO): Likewise.
2000-01-05 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x.md (*addqi3_noclobber_reload): Ensure that CC never

86
gcc/config/c4x/c4x.c
View File

@ -1,5 +1,5 @@
/* Subroutines for assembler code output on the TMS320C[34]x
Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
Copyright (C) 1994-99, 2000 Free Software Foundation, Inc.
Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
@ -332,22 +332,22 @@ c4x_hard_regno_mode_ok (regno, mode)
case Pmode: /* Pointer (24/32 bits) */
#endif
case QImode: /* Integer (32 bits) */
return IS_INT_REG (regno);
return IS_INT_REGNO (regno);
case QFmode: /* Float, Double (32 bits) */
case HFmode: /* Long Double (40 bits) */
return IS_EXT_REG (regno);
return IS_EXT_REGNO (regno);
case CCmode: /* Condition Codes */
case CC_NOOVmode: /* Condition Codes */
return IS_ST_REG (regno);
return IS_ST_REGNO (regno);
case HImode: /* Long Long (64 bits) */
/* We need two registers to store long longs. Note that
it is much easier to constrain the first register
to start on an even boundary. */
return IS_INT_REG (regno)
&& IS_INT_REG (regno + 1)
return IS_INT_REGNO (regno)
&& IS_INT_REGNO (regno + 1)
&& (regno & 1) == 0;
default:
@ -636,13 +636,13 @@ c4x_isr_reg_used_p (regno)
{
/* Don't save/restore FP or ST, we handle them separately. */
if (regno == FRAME_POINTER_REGNUM
|| IS_ST_REG (regno))
|| IS_ST_REGNO (regno))
return 0;
/* We could be a little smarter abut saving/restoring DP.
We'll only save if for the big memory model or if
we're paranoid. ;-) */
if (IS_DP_REG (regno))
if (IS_DP_REGNO (regno))
return ! TARGET_SMALL || TARGET_PARANOID;
/* Only save/restore regs in leaf function that are used. */
@ -652,7 +652,7 @@ c4x_isr_reg_used_p (regno)
/* Only save/restore regs that are used by the ISR and regs
that are likely to be used by functions the ISR calls
if they are not fixed. */
return IS_EXT_REG (regno)
return IS_EXT_REGNO (regno)
|| ((regs_ever_live[regno] || call_used_regs[regno])
&& fixed_regs[regno] == 0);
}
@ -757,7 +757,7 @@ c4x_function_prologue (file, size)
if (c4x_isr_reg_used_p (regno))
{
fprintf (file, "\tpush\t%s\n", reg_names[regno]);
if (IS_EXT_REG (regno)) /* save 32MSB of R0--R11 */
if (IS_EXT_REGNO (regno)) /* save 32MSB of R0--R11 */
fprintf (file, "\tpushf\t%s\n", float_reg_names[regno]);
}
}
@ -890,7 +890,7 @@ c4x_function_epilogue (file, size)
{
if (! c4x_isr_reg_used_p (regno))
continue;
if (IS_EXT_REG (regno))
if (IS_EXT_REGNO (regno))
fprintf (file, "\tpopf\t%s\n", float_reg_names[regno]);
fprintf (file, "\tpop\t%s\n", reg_names[regno]);
}
@ -1371,7 +1371,7 @@ c4x_check_legit_addr (mode, addr, strict)
{
base = op0; /* base + index */
indx = op1;
if (IS_INDEX_REGNO (base) || IS_ADDR_REGNO (indx))
if (IS_INDEX_REG (base) || IS_ADDR_REG (indx))
{
base = op1;
indx = op0;
@ -1466,7 +1466,7 @@ c4x_check_legit_addr (mode, addr, strict)
return 1;
if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
return 0;
else if (! strict && ! IS_ADDR_OR_PSEUDO_REGNO (base))
else if (! strict && ! IS_ADDR_OR_PSEUDO_REG (base))
return 0;
}
@ -1477,7 +1477,7 @@ c4x_check_legit_addr (mode, addr, strict)
return 0;
if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
return 0;
else if (! strict && ! IS_INDEX_OR_PSEUDO_REGNO (indx))
else if (! strict && ! IS_INDEX_OR_PSEUDO_REG (indx))
return 0;
}
@ -1984,7 +1984,7 @@ c4x_print_operand_address (file, addr)
{
if (REG_P (op1))
{
if (IS_INDEX_REGNO (op0))
if (IS_INDEX_REG (op0))
{
fprintf (file, "*+%s(%s)",
reg_names[REGNO (op1)],
@ -2238,7 +2238,7 @@ static int
c4x_a_register (op)
rtx op;
{
return REG_P (op) && IS_ADDR_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_ADDR_OR_PSEUDO_REG (op);
}
@ -2246,7 +2246,7 @@ static int
c4x_x_register (op)
rtx op;
{
return REG_P (op) && IS_INDEX_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_INDEX_OR_PSEUDO_REG (op);
}
@ -2468,7 +2468,7 @@ c4x_R_indirect (op)
switch (GET_CODE (op))
{
case REG:
return IS_ADDR_OR_PSEUDO_REGNO (op);
return IS_ADDR_OR_PSEUDO_REG (op);
case PLUS:
{
@ -2477,12 +2477,12 @@ c4x_R_indirect (op)
/* HImode and HFmode must be offsettable. */
if (mode == HImode || mode == HFmode)
return IS_ADDR_OR_PSEUDO_REGNO (op0)
return IS_ADDR_OR_PSEUDO_REG (op0)
&& GET_CODE (op1) == CONST_INT
&& IS_UINT5_CONST (INTVAL (op1) + 1);
return REG_P (op0)
&& IS_ADDR_OR_PSEUDO_REGNO (op0)
&& IS_ADDR_OR_PSEUDO_REG (op0)
&& GET_CODE (op1) == CONST_INT
&& IS_UINT5_CONST (INTVAL (op1));
}
@ -2580,7 +2580,7 @@ c4x_S_indirect (op)
op = XEXP (op, 0);
case REG:
return IS_ADDR_OR_PSEUDO_REGNO (op);
return IS_ADDR_OR_PSEUDO_REG (op);
case PRE_MODIFY:
case POST_MODIFY:
@ -2597,8 +2597,8 @@ c4x_S_indirect (op)
op0 = XEXP (op1, 0);
op1 = XEXP (op1, 1);
return REG_P (op0) && IS_ADDR_OR_PSEUDO_REGNO (op0)
&& REG_P (op1) && IS_INDEX_OR_PSEUDO_REGNO (op1);
return REG_P (op0) && IS_ADDR_OR_PSEUDO_REG (op0)
&& REG_P (op1) && IS_INDEX_OR_PSEUDO_REG (op1);
/* pre or post_modify with a displacement of 0 or 1
should not be generated. */
}
@ -2612,17 +2612,17 @@ c4x_S_indirect (op)
{
/* HImode and HFmode must be offsettable. */
if (mode == HImode || mode == HFmode)
return IS_ADDR_OR_PSEUDO_REGNO (op0)
return IS_ADDR_OR_PSEUDO_REG (op0)
&& GET_CODE (op1) == CONST_INT
&& IS_DISP1_OFF_CONST (INTVAL (op1));
if (REG_P (op1))
return (IS_INDEX_OR_PSEUDO_REGNO (op1)
&& IS_ADDR_OR_PSEUDO_REGNO (op0))
|| (IS_ADDR_OR_PSEUDO_REGNO (op1)
&& IS_INDEX_OR_PSEUDO_REGNO (op0));
return (IS_INDEX_OR_PSEUDO_REG (op1)
&& IS_ADDR_OR_PSEUDO_REG (op0))
|| (IS_ADDR_OR_PSEUDO_REG (op1)
&& IS_INDEX_OR_PSEUDO_REG (op0));
return IS_ADDR_OR_PSEUDO_REGNO (op0)
return IS_ADDR_OR_PSEUDO_REG (op0)
&& GET_CODE (op1) == CONST_INT
&& IS_DISP1_CONST (INTVAL (op1));
}
@ -2897,7 +2897,7 @@ r0r1_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_R0R1_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
}
@ -2912,7 +2912,7 @@ r2r3_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_R2R3_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
}
@ -2927,7 +2927,7 @@ ext_low_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
}
@ -2944,7 +2944,7 @@ ext_reg_operand (op, mode)
op = SUBREG_REG (op);
if (! REG_P (op))
return 0;
return IS_EXT_OR_PSEUDO_REGNO (op);
return IS_EXT_OR_PSEUDO_REG (op);
}
@ -2959,7 +2959,7 @@ std_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_STD_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
}
@ -2998,7 +2998,7 @@ dp_reg_operand (op, mode)
rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_DP_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
}
@ -3009,7 +3009,7 @@ sp_reg_operand (op, mode)
rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_SP_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
}
@ -3020,7 +3020,7 @@ st_reg_operand (op, mode)
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_ST_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
}
@ -3031,7 +3031,7 @@ rc_reg_operand (op, mode)
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_RC_OR_PSEUDO_REGNO (op);
return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
}
@ -3832,7 +3832,7 @@ group1_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_GROUP1_REG (REGNO (op));
return REG_P (op) && IS_GROUP1_REG (op);
}
@ -3852,11 +3852,11 @@ group1_mem_operand (op, mode)
rtx op0 = XEXP (op, 0);
rtx op1 = XEXP (op, 1);
if (((GET_CODE (op0) == REG) && IS_GROUP1_REGNO (op0))
|| ((GET_CODE (op1) == REG) && IS_GROUP1_REGNO (op1)))
if (((GET_CODE (op0) == REG) && IS_GROUP1_REG (op0))
|| ((GET_CODE (op1) == REG) && IS_GROUP1_REG (op1)))
return 1;
}
else if ((REG_P (op)) && IS_GROUP1_REGNO (op))
else if ((REG_P (op)) && IS_GROUP1_REG (op))
return 1;
}
@ -3875,7 +3875,7 @@ arx_reg_operand (op, mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return REG_P (op) && IS_ADDR_REGNO (op);
return REG_P (op) && IS_ADDR_REG (op);
}

165
gcc/config/c4x/c4x.h
View File

@ -1,5 +1,5 @@
/* Definitions of target machine for GNU compiler. TMS320C[34]x
Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
Copyright (C) 1994-99, 2000 Free Software Foundation, Inc.
Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
@ -362,9 +362,9 @@ extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
#define REAL_ARITHMETIC
/* Define register numbers */
/* Define register numbers. */
/* Extended-precision registers */
/* Extended-precision registers. */
#define R0_REGNO 0
#define R1_REGNO 1
@ -375,7 +375,7 @@ extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
#define R6_REGNO 6
#define R7_REGNO 7
/* Auxiliary (address) registers */
/* Auxiliary (address) registers. */
#define AR0_REGNO 8
#define AR1_REGNO 9
@ -386,118 +386,123 @@ extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
#define AR6_REGNO 14
#define AR7_REGNO 15
/* Data page register */
/* Data page register. */
#define DP_REGNO 16
/* Index registers */
/* Index registers. */
#define IR0_REGNO 17
#define IR1_REGNO 18
/* Block size register */
/* Block size register. */
#define BK_REGNO 19
/* Stack pointer */
/* Stack pointer. */
#define SP_REGNO 20
/* Status register */
/* Status register. */
#define ST_REGNO 21
/* Misc. interrupt registers */
/* Misc. interrupt registers. */
#define DIE_REGNO 22 /* C4x only */
#define IE_REGNO 22 /* C3x only */
#define IIE_REGNO 23 /* C4x only */
#define IF_REGNO 23 /* C3x only */
#define IIF_REGNO 24 /* C4x only */
#define IOF_REGNO 24 /* C3x only */
#define DIE_REGNO 22 /* C4x only. */
#define IE_REGNO 22 /* C3x only. */
#define IIE_REGNO 23 /* C4x only. */
#define IF_REGNO 23 /* C3x only. */
#define IIF_REGNO 24 /* C4x only. */
#define IOF_REGNO 24 /* C3x only. */
/* Repeat block registers */
/* Repeat block registers. */
#define RS_REGNO 25
#define RE_REGNO 26
#define RC_REGNO 27
/* Additional extended-precision registers */
/* Additional extended-precision registers. */
#define R8_REGNO 28 /* C4x only */
#define R9_REGNO 29 /* C4x only */
#define R10_REGNO 30 /* C4x only */
#define R11_REGNO 31 /* C4x only */
#define R8_REGNO 28 /* C4x only. */
#define R9_REGNO 29 /* C4x only. */
#define R10_REGNO 30 /* C4x only. */
#define R11_REGNO 31 /* C4x only. */
#define FIRST_PSEUDO_REGISTER 32
/* Extended precision registers (low set) */
/* Extended precision registers (low set). */
#define IS_R0R1_REG(r) ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
#define IS_R2R3_REG(r) ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
#define IS_EXT_LOW_REG(r) ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
#define IS_R0R1_REGNO(r) ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
#define IS_R2R3_REGNO(r) ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
#define IS_EXT_LOW_REGNO(r) ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
/* Extended precision registers (high set) */
/* Extended precision registers (high set). */
#define IS_EXT_HIGH_REG(r) (! TARGET_C3X \
#define IS_EXT_HIGH_REGNO(r) (! TARGET_C3X \
&& ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
/* Address registers */
/* Address registers. */
#define IS_AUX_REG(r) (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
#define IS_ADDR_REG(r) IS_AUX_REG(r)
#define IS_DP_REG(r) ((r) == DP_REGNO)
#define IS_INDEX_REG(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
#define IS_SP_REG(r) ((r) == SP_REGNO)
#define IS_BK_REG(r) (TARGET_BK && (r) == BK_REGNO)
#define IS_AUX_REGNO(r) (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
#define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
#define IS_DP_REGNO(r) ((r) == DP_REGNO)
#define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
#define IS_SP_REGNO(r) ((r) == SP_REGNO)
#define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
/* Misc registers */
/* Misc registers. */
#define IS_ST_REG(r) ((r) == ST_REGNO)
#define IS_RC_REG(r) ((r) == RC_REGNO)
#define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
#define IS_ST_REGNO(r) ((r) == ST_REGNO)
#define IS_RC_REGNO(r) ((r) == RC_REGNO)
#define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
/* Composite register sets */
/* Composite register sets. */
#define IS_ADDR_OR_INDEX_REG(r) (IS_ADDR_REG(r) || IS_INDEX_REG(r))
#define IS_EXT_REG(r) (IS_EXT_LOW_REG(r) || IS_EXT_HIGH_REG(r))
#define IS_STD_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_REPEAT_REG(r) \
|| IS_SP_REG(r) || IS_BK_REG(r))
#define IS_INT_REG(r) (IS_EXT_REG(r) || IS_STD_REG(r))
#define IS_GROUP1_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_BK_REG(r))
#define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
#define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
#define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
|| IS_REPEAT_REGNO(r) \
|| IS_SP_REGNO(r) \
|| IS_BK_REGNO(r))
#define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
#define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
#define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
#define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
|| IS_PSEUDO_REGNO(r))
#define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_PSEUDO_REG(r) ((r) >= FIRST_PSEUDO_REGISTER)
#define IS_R0R1_OR_PSEUDO_REG(r) (IS_R0R1_REG(r) || IS_PSEUDO_REG(r))
#define IS_R2R3_OR_PSEUDO_REG(r) (IS_R2R3_REG(r) || IS_PSEUDO_REG(r))
#define IS_EXT_OR_PSEUDO_REG(r) (IS_EXT_REG(r) || IS_PSEUDO_REG(r))
#define IS_STD_OR_PSEUDO_REG(r) (IS_STD_REG(r) || IS_PSEUDO_REG(r))
#define IS_INT_OR_PSEUDO_REG(r) (IS_INT_REG(r) || IS_PSEUDO_REG(r))
#define IS_ADDR_OR_PSEUDO_REG(r) (IS_ADDR_REG(r) || IS_PSEUDO_REG(r))
#define IS_INDEX_OR_PSEUDO_REG(r) (IS_INDEX_REG(r) || IS_PSEUDO_REG(r))
#define IS_EXT_LOW_OR_PSEUDO_REG(r) (IS_EXT_LOW_REG(r) || IS_PSEUDO_REG(r))
#define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r))
#define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r))
#define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r))
#define IS_RC_OR_PSEUDO_REG(r) (IS_RC_REG(r) || IS_PSEUDO_REG(r))
#define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
#define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
#define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
#define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
#define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
#define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
#define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
#define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op)))
#define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op)))
#define IS_INDEX_REGNO(op) (IS_INDEX_REG(REGNO(op)))
#define IS_GROUP1_REGNO(r) (IS_GROUP1_REG(REGNO(op)))
#define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_R0R1_OR_PSEUDO_REGNO(op) (IS_R0R1_OR_PSEUDO_REG(REGNO(op)))
#define IS_R2R3_OR_PSEUDO_REGNO(op) (IS_R2R3_OR_PSEUDO_REG(REGNO(op)))
#define IS_EXT_OR_PSEUDO_REGNO(op) (IS_EXT_OR_PSEUDO_REG(REGNO(op)))
#define IS_STD_OR_PSEUDO_REGNO(op) (IS_STD_OR_PSEUDO_REG(REGNO(op)))
#define IS_EXT_LOW_OR_PSEUDO_REGNO(op) (IS_EXT_LOW_OR_PSEUDO_REG(REGNO(op)))
#define IS_INT_OR_PSEUDO_REGNO(op) (IS_INT_OR_PSEUDO_REG(REGNO(op)))
#define IS_ADDR_OR_PSEUDO_REGNO(op) (IS_ADDR_OR_PSEUDO_REG(REGNO(op)))
#define IS_INDEX_OR_PSEUDO_REGNO(op) (IS_INDEX_OR_PSEUDO_REG(REGNO(op)))
#define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op)))
#define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op)))
#define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op)))
#define IS_RC_OR_PSEUDO_REGNO(op) (IS_RC_OR_PSEUDO_REG(REGNO(op)))
#define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
@ -801,10 +806,10 @@ enum reg_class
has been allocated, which happens in local-alloc.c. */
#define REGNO_OK_FOR_BASE_P(REGNO) \
(IS_ADDR_REG(REGNO) || IS_ADDR_REG((unsigned)reg_renumber[REGNO]))
(IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
#define REGNO_OK_FOR_INDEX_P(REGNO) \
(IS_INDEX_REG(REGNO) || IS_INDEX_REG((unsigned)reg_renumber[REGNO]))
(IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
@ -1575,11 +1580,11 @@ CUMULATIVE_ARGS;
/* Nonzero if X is a hard or pseudo reg that can be used as an base. */
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(REGNO(X))
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
/* Nonzero if X is a hard or pseudo reg that can be used as an index. */
#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(REGNO(X))
#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \

12
gcc/config/c4x/c4x.md
View File

@ -1344,9 +1344,9 @@
/* The lda instruction cannot use the same register as source
and destination. */
if (! TARGET_C3X && which_alternative == 1
&& ( IS_ADDR_REG (REGNO (operands[0]))
|| IS_INDEX_REG (REGNO (operands[0]))
|| IS_SP_REG (REGNO (operands[0])))
&& ( IS_ADDR_REG (operands[0])
|| IS_INDEX_REG (operands[0])
|| IS_SP_REG (operands[0]))
&& (REGNO (operands[0]) != REGNO (operands[1])))
return \"lda\\t%1,%0\";
return \"ldiu\\t%1,%0\";
@ -1762,8 +1762,8 @@
""
"legitimize_operands (PLUS, operands, QImode);
if (reload_in_progress
|| (! IS_PSEUDO_REGNO (operands[0])
&& ! IS_EXT_REG (REGNO (operands[0]))))
|| (! IS_PSEUDO_REG (operands[0])
&& ! IS_EXT_REG (operands[0])))
{
emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
DONE;
@ -1890,7 +1890,7 @@
(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))]
"reload_in_progress"
"*
if (IS_STD_REG (REGNO (operands[0])))
if (IS_STD_REG (operands[0]))
{
if (which_alternative == 0)
return \"addi\\t%2,%0\";