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[AArch64] Split X-reg UBFX into W-reg LSR when possible

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* config/aarch64/aarch64.md: New define_split above insv<mode>.

	* gcc.target/aarch64/ubfx_lsr_1.c: New test.

From-SVN: r243755
This commit is contained in:
Kyrylo Tkachov 2016-12-16 16:24:26 +00:00 committed by Kyrylo Tkachov
parent 17f3bb6d25
commit bcb036c515
4 changed files with 42 additions and 0 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md: New define_split above insv<mode>.
2016-12-16 Jakub Jelinek <jakub@redhat.com>
PR c/78408

20
gcc/config/aarch64/aarch64.md
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@ -4325,6 +4325,26 @@
[(set_attr "type" "bfx")]
)
;; When the bit position and width add up to 32 we can use a W-reg LSR
;; instruction taking advantage of the implicit zero-extension of the X-reg.
(define_split
[(set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_operand:DI 1 "register_operand")
(match_operand 2
"aarch64_simd_shift_imm_offset_di")
(match_operand 3
"aarch64_simd_shift_imm_di")))]
"IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1,
GET_MODE_BITSIZE (DImode) - 1)
&& (INTVAL (operands[2]) + INTVAL (operands[3]))
== GET_MODE_BITSIZE (SImode)"
[(set (match_dup 0)
(zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))]
{
operands[4] = gen_lowpart (SImode, operands[1]);
}
)
;; Bitfield Insert (insv)
(define_expand "insv<mode>"
[(set (zero_extract:GPI (match_operand:GPI 0 "register_operand")

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/ubfx_lsr_1.c: New test.
2016-12-16 Jakub Jelinek <jakub@redhat.com>
PR c/78408

14
gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c Normal file
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/* { dg-do compile } */
/* { dg-options "-O2" } */
/* Check that an X-reg UBFX can be simplified into a W-reg LSR. */
int
f (unsigned long long x)
{
x = (x >> 24) & 255;
return x + 1;
}
/* { dg-final { scan-assembler "lsr\tw" } } */
/* { dg-final { scan-assembler-not "ubfx\tx" } } */