i386.md (ffs<mode>2): Generate CCCmode flags register for TARGET_BMI.
* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register for TARGET_BMI. (ffssi2_no_cmove): Ditto. (*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern. (*tzcnt<mode>_1_falsedep): New insn pattern. (LT_ZCNT): New mode iterator. (lt_zcnt): New mode attribute. (lt_zcnt_type): New mode attribute. (<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and lzcnt_<mode> using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from *bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1 using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>_falsedep): Macroize insn from *bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode> and *lzcnt_<mode> using LT_ZCNT mode iterator. * config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16) (__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs): Update for rename. From-SVN: r243727
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
f3e1097bc6
commit
bdb5177687
@ -1,3 +1,28 @@
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2016-12-15 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register
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for TARGET_BMI.
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(ffssi2_no_cmove): Ditto.
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(*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern.
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(*tzcnt<mode>_1_falsedep): New insn pattern.
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(LT_ZCNT): New mode iterator.
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(lt_zcnt): New mode attribute.
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(lt_zcnt_type): New mode attribute.
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(<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and
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lzcnt_<mode> using LT_ZCNT mode iterator.
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(*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from
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*bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1
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using LT_ZCNT mode iterator.
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(*<lt_zcnt>_<mode>_falsedep): Macroize insn from
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*bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep
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using LT_ZCNT mode iterator.
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(*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode>
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and *lzcnt_<mode> using LT_ZCNT mode iterator.
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* config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16)
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(__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs):
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Update for rename.
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2016-12-15 Jakub Jelinek <jakub@redhat.com>
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* ipa-cp.c (class ipcp_bits_lattice): Formatting fixes.
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@ -1197,11 +1197,11 @@ BDESC (OPTION_MASK_ISA_LZCNT | OPTION_MASK_ISA_64BIT, CODE_FOR_lzcnt_di, "__buil
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
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BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64)
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_hi, "__builtin_ia32_tzcnt_u16", IX86_BUILTIN_TZCNT16, UNKNOWN, (int) UINT16_FTYPE_UINT16)
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_hi, "__builtin_ia32_tzcnt_u16", IX86_BUILTIN_TZCNT16, UNKNOWN, (int) UINT16_FTYPE_UINT16)
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/* Same as above, for backward compatibility. */
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_hi, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16)
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_si, "__builtin_ia32_tzcnt_u32", IX86_BUILTIN_TZCNT32, UNKNOWN, (int) UINT_FTYPE_UINT)
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BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_bmi_tzcnt_di, "__builtin_ia32_tzcnt_u64", IX86_BUILTIN_TZCNT64, UNKNOWN, (int) UINT64_FTYPE_UINT64)
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_hi, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16)
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BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_si, "__builtin_ia32_tzcnt_u32", IX86_BUILTIN_TZCNT32, UNKNOWN, (int) UINT_FTYPE_UINT)
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BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_tzcnt_di, "__builtin_ia32_tzcnt_u64", IX86_BUILTIN_TZCNT64, UNKNOWN, (int) UINT64_FTYPE_UINT64)
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/* TBM */
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BDESC (OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
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@ -12534,8 +12534,7 @@
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DONE;
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}
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flags_mode
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= (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
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flags_mode = TARGET_BMI ? CCCmode : CCZmode;
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operands[2] = gen_reg_rtx (<MODE>mode);
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operands[3] = gen_rtx_REG (flags_mode, FLAGS_REG);
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@ -12561,8 +12560,7 @@
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(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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machine_mode flags_mode
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= (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
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machine_mode flags_mode = TARGET_BMI ? CCCmode : CCZmode;
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operands[3] = gen_lowpart (QImode, operands[2]);
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operands[4] = gen_rtx_REG (flags_mode, FLAGS_REG);
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@ -12571,13 +12569,53 @@
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ix86_expand_clear (operands[2]);
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})
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; False dependency happens when destination is only updated by tzcnt,
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; lzcnt or popcnt. There is no false dependency when destination is
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; also used in source.
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(define_insn_and_split "*tzcnt<mode>_1_falsedep_1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
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(const_int 0)))
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(set (match_operand:SWI48 0 "register_operand" "=r")
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(ctz:SWI48 (match_dup 1)))]
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"TARGET_BMI
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&& TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC (match_dup 1) (const_int 0)))
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(set (match_dup 0)
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(ctz:SWI48 (match_dup 1)))
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(unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)])]
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{
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if (!reg_mentioned_p (operands[0], operands[1]))
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ix86_expand_clear (operands[0]);
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})
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(define_insn "*tzcnt<mode>_1_falsedep"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
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(const_int 0)))
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(set (match_operand:SWI48 0 "register_operand" "=r")
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(ctz:SWI48 (match_dup 1)))
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(unspec [(match_operand:SWI48 2 "register_operand" "0")]
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UNSPEC_INSN_FALSE_DEP)]
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"TARGET_BMI"
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"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
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[(set_attr "type" "alu1")
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(set_attr "prefix_0f" "1")
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(set_attr "prefix_rep" "1")
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(set_attr "btver2_decode" "double")
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(set_attr "mode" "<MODE>")])
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(define_insn "*tzcnt<mode>_1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
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(const_int 0)))
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(set (match_operand:SWI48 0 "register_operand" "=r")
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(ctz:SWI48 (match_dup 1)))]
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"TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI"
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"TARGET_BMI"
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"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
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[(set_attr "type" "alu1")
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(set_attr "prefix_0f" "1")
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@ -12619,7 +12657,7 @@
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{
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rtx tmp = gen_reg_rtx (HImode);
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emit_insn (gen_bmi_tzcnt_hi (tmp, operands[1]));
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emit_insn (gen_tzcnt_hi (tmp, operands[1]));
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emit_insn (gen_zero_extendhisi2 (operands[0], tmp));
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DONE;
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})
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@ -12695,68 +12733,41 @@
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(const_string "0")))
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(set_attr "mode" "<MODE>")])
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;; Version of tzcnt that is expanded from intrinsics. This version provides
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;; operand size as output when source operand is zero.
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(define_expand "bmi_tzcnt_<mode>"
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[(parallel
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[(set (match_operand:SWI248 0 "register_operand")
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(unspec:SWI248
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[(match_operand:SWI248 1 "nonimmediate_operand")]
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UNSPEC_TZCNT))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_BMI")
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; False dependency happens when destination is only updated by tzcnt,
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; lzcnt or popcnt. There is no false dependency when destination is
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; also used in source.
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(define_insn_and_split "*bmi_tzcnt_<mode>_falsedep_1"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(unspec:SWI48
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
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UNSPEC_TZCNT))
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(define_insn "bsr_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (const_int 63)
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(clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI
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&& TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (match_dup 0)
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(unspec:SWI48 [(match_dup 1)] UNSPEC_TZCNT))
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(unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
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(clobber (reg:CC FLAGS_REG))])]
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{
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if (!reg_mentioned_p (operands[0], operands[1]))
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ix86_expand_clear (operands[0]);
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})
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(define_insn "*bmi_tzcnt_<mode>_falsedep"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(unspec:SWI48
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
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UNSPEC_TZCNT))
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(unspec [(match_operand:SWI48 2 "register_operand" "0")]
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UNSPEC_INSN_FALSE_DEP)
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
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"TARGET_64BIT"
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"bsr{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "alu1")
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(set_attr "prefix_0f" "1")
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(set_attr "prefix_rep" "1")
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(set_attr "mode" "<MODE>")])
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(set_attr "znver1_decode" "vector")
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(set_attr "mode" "DI")])
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(define_insn "*bmi_tzcnt_<mode>"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(unspec:SWI248
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[(match_operand:SWI248 1 "nonimmediate_operand" "rm")]
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UNSPEC_TZCNT))
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(define_insn "bsr"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (const_int 31)
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(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
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""
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"bsr{l}\t{%1, %0|%0, %1}"
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[(set_attr "type" "alu1")
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(set_attr "prefix_0f" "1")
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(set_attr "prefix_rep" "1")
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(set_attr "mode" "<MODE>")])
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(set_attr "znver1_decode" "vector")
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(set_attr "mode" "SI")])
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(define_insn "*bsrhi"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(minus:HI (const_int 15)
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(clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC FLAGS_REG))]
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""
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"bsr{w}\t{%1, %0|%0, %1}"
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[(set_attr "type" "alu1")
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(set_attr "prefix_0f" "1")
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(set_attr "znver1_decode" "vector")
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(set_attr "mode" "HI")])
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(define_expand "clz<mode>2"
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[(parallel
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@ -12778,14 +12789,6 @@
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operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
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})
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(define_expand "clz<mode>2_lzcnt"
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[(parallel
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[(set (match_operand:SWI48 0 "register_operand")
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(clz:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_LZCNT")
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(define_insn_and_split "*clzhi2"
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[(set (match_operand:SI 0 "register_operand")
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(clz:SI
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@ -12839,9 +12842,10 @@
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(set_attr "type" "bitmanip")
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(set_attr "mode" "<MODE>")])
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(define_insn "*clz<mode>2_lzcnt"
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(define_insn "clz<mode>2_lzcnt"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(clz:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
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(clz:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "rm")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_LZCNT"
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"lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
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@ -12849,34 +12853,42 @@
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(set_attr "type" "bitmanip")
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(set_attr "mode" "<MODE>")])
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;; Version of lzcnt that is expanded from intrinsics. This version provides
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;; operand size as output when source operand is zero.
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(define_int_iterator LT_ZCNT
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[(UNSPEC_TZCNT "TARGET_BMI")
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(UNSPEC_LZCNT "TARGET_LZCNT")])
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(define_expand "lzcnt_<mode>"
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(define_int_attr lt_zcnt
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[(UNSPEC_TZCNT "tzcnt")
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(UNSPEC_LZCNT "lzcnt")])
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(define_int_attr lt_zcnt_type
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[(UNSPEC_TZCNT "alu1")
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(UNSPEC_LZCNT "bitmanip")])
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;; Version of lzcnt/tzcnt that is expanded from intrinsics. This version
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;; provides operand size as output when source operand is zero.
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(define_expand "<lt_zcnt>_<mode>"
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[(parallel
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[(set (match_operand:SWI248 0 "register_operand")
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(unspec:SWI248
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[(match_operand:SWI248 1 "nonimmediate_operand")]
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UNSPEC_LZCNT))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_LZCNT")
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[(match_operand:SWI248 1 "nonimmediate_operand")] LT_ZCNT))
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(clobber (reg:CC FLAGS_REG))])])
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; False dependency happens when destination is only updated by tzcnt,
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; lzcnt or popcnt. There is no false dependency when destination is
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; also used in source.
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(define_insn_and_split "*lzcnt_<mode>_falsedep_1"
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(define_insn_and_split "*<lt_zcnt>_<mode>_falsedep_1"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(unspec:SWI48
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
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UNSPEC_LZCNT))
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")] LT_ZCNT))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_LZCNT
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&& TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
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"TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (match_dup 0)
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(unspec:SWI48 [(match_dup 1)] UNSPEC_LZCNT))
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(unspec:SWI48 [(match_dup 1)] LT_ZCNT))
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(unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
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(clobber (reg:CC FLAGS_REG))])]
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{
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@ -12884,30 +12896,28 @@
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ix86_expand_clear (operands[0]);
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})
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(define_insn "*lzcnt_<mode>_falsedep"
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(define_insn "*<lt_zcnt>_<mode>_falsedep"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(unspec:SWI48
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
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UNSPEC_LZCNT))
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[(match_operand:SWI48 1 "nonimmediate_operand" "rm")] LT_ZCNT))
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(unspec [(match_operand:SWI48 2 "register_operand" "0")]
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UNSPEC_INSN_FALSE_DEP)
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_LZCNT"
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"lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
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[(set_attr "type" "alu1")
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""
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"<lt_zcnt>{<imodesuffix>}\t{%1, %0|%0, %1}"
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[(set_attr "type" "<lt_zcnt_type>")
|
||||
(set_attr "prefix_0f" "1")
|
||||
(set_attr "prefix_rep" "1")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*lzcnt_<mode>"
|
||||
(define_insn "*<lt_zcnt>_<mode>"
|
||||
[(set (match_operand:SWI248 0 "register_operand" "=r")
|
||||
(unspec:SWI248
|
||||
[(match_operand:SWI248 1 "nonimmediate_operand" "rm")]
|
||||
UNSPEC_LZCNT))
|
||||
[(match_operand:SWI248 1 "nonimmediate_operand" "rm")] LT_ZCNT))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_LZCNT"
|
||||
"lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "alu1")
|
||||
""
|
||||
"<lt_zcnt>{<imodesuffix>}\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "<lt_zcnt_type>")
|
||||
(set_attr "prefix_0f" "1")
|
||||
(set_attr "prefix_rep" "1")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
@ -13206,42 +13216,6 @@
|
||||
[(set_attr "type" "bitmanip")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "bsr_rex64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(minus:DI (const_int 63)
|
||||
(clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT"
|
||||
"bsr{q}\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "alu1")
|
||||
(set_attr "prefix_0f" "1")
|
||||
(set_attr "znver1_decode" "vector")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "bsr"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(minus:SI (const_int 31)
|
||||
(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
""
|
||||
"bsr{l}\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "alu1")
|
||||
(set_attr "prefix_0f" "1")
|
||||
(set_attr "znver1_decode" "vector")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*bsrhi"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(minus:HI (const_int 15)
|
||||
(clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
""
|
||||
"bsr{w}\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "alu1")
|
||||
(set_attr "prefix_0f" "1")
|
||||
(set_attr "znver1_decode" "vector")
|
||||
(set_attr "mode" "HI")])
|
||||
|
||||
(define_expand "popcount<mode>2"
|
||||
[(parallel
|
||||
[(set (match_operand:SWI248 0 "register_operand")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user