rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit floating point modes that can go in vector registers.
2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit
floating point modes that can go in vector registers.
(MODES_TIEABLE_P): Move tests for vector modes before tests for
scalar floating point, so that IEEE 128-bit floating point that
can go in vector registers bind with vectors and not FP.
(struct rs6000_args): Add libcall field.
* config/rs6000/rs6000.opt (-mfloat128-*): Delete -mfloat128-none
and -mfloat128-software switches. Replace them with a binary
-mfloat128 switch.
(-mfloat128): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
128-bit floating point types in GPRs, even if the appropriate
option enabling the type was not used.
(rs6000_debug_reg_global): Remove -mfloat128-{software,none}
debugging.
(rs6000_setup_reg_addr_masks): Do not allow pre-increment and
pre-decrement on IEEE 128-bit floating point values.
(rs6000_init_hard_regno_mode_ok): Change test for whether TFmode
is IEEE 128-bit floating point.
(rs6000_init_hard_regno_mode_ok): Add reload handlers for IEEE
128-bit floating point types that can go in vector registers.
(rs6000_option_override_internal): Change -mfloat128-none and
-mfloat128-software to -mfloat128, and move code to be near other
VSX option handling.
(rs6000_option_override_internal): Disable -mfloat128 if we don't
have the Altivec ABI.
(rs6000_init_builtins): Don't make TFmode use either IFmode or
KFmode floating point nodes. Instead, have three separate nodes.
(rs6000_scalar_mode_supported_p): Add support for IFmode to allow
eventually moving the long double default to IEEE 128-bit floating
point.
(rs6000_opt_masks): Add -mfloat128.
(struct rs6000_opt_var): Fix typo in comment.
(init_cumulative_args): Initialize libcall field in
CUMULATIVE_ARGS.
(rs6000_function_arg): Treat library functions as if they had
prototypes to prevent IEEE 128-bit support functions from passing
arguments in both GPRs and vector registers.
(rs6000_arg_partial_bytes): Likewise.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mfloat128 as
an option that can be turned on via -mcpu=<xxx>.
* config/rs6000/rs6000-opts.h (enum float128_type_t): Delete, no
longer used.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
__FLOAT128__ if -mfloat128. Define __LONG_DOUBLE_IEEE128__ if long
double is IEEE 128-bit. Define __LONG_DOUBLE_IBM128__ if long
double is IBM extended double.
* config/rs6000/predicates.md (reg_or_indexed_operand): Allow
SUBREGs.
From-SVN: r229545
This commit is contained in:
Michael Meissner
Michael Meissner
parent
721be0f47c
commit
bdb60a10ac
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@ -1,3 +1,61 @@
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2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit
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floating point modes that can go in vector registers.
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(MODES_TIEABLE_P): Move tests for vector modes before tests for
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scalar floating point, so that IEEE 128-bit floating point that
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can go in vector registers bind with vectors and not FP.
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(struct rs6000_args): Add libcall field.
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* config/rs6000/rs6000.opt (-mfloat128-*): Delete -mfloat128-none
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and -mfloat128-software switches. Replace them with a binary
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-mfloat128 switch.
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(-mfloat128): Likewise.
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* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
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128-bit floating point types in GPRs, even if the appropriate
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option enabling the type was not used.
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(rs6000_debug_reg_global): Remove -mfloat128-{software,none}
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debugging.
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(rs6000_setup_reg_addr_masks): Do not allow pre-increment and
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pre-decrement on IEEE 128-bit floating point values.
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(rs6000_init_hard_regno_mode_ok): Change test for whether TFmode
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is IEEE 128-bit floating point.
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(rs6000_init_hard_regno_mode_ok): Add reload handlers for IEEE
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128-bit floating point types that can go in vector registers.
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(rs6000_option_override_internal): Change -mfloat128-none and
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-mfloat128-software to -mfloat128, and move code to be near other
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VSX option handling.
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(rs6000_option_override_internal): Disable -mfloat128 if we don't
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have the Altivec ABI.
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(rs6000_init_builtins): Don't make TFmode use either IFmode or
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KFmode floating point nodes. Instead, have three separate nodes.
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(rs6000_scalar_mode_supported_p): Add support for IFmode to allow
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eventually moving the long double default to IEEE 128-bit floating
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point.
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(rs6000_opt_masks): Add -mfloat128.
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(struct rs6000_opt_var): Fix typo in comment.
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(init_cumulative_args): Initialize libcall field in
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CUMULATIVE_ARGS.
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(rs6000_function_arg): Treat library functions as if they had
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prototypes to prevent IEEE 128-bit support functions from passing
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arguments in both GPRs and vector registers.
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(rs6000_arg_partial_bytes): Likewise.
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* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mfloat128 as
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an option that can be turned on via -mcpu=<xxx>.
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* config/rs6000/rs6000-opts.h (enum float128_type_t): Delete, no
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longer used.
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* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
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__FLOAT128__ if -mfloat128. Define __LONG_DOUBLE_IEEE128__ if long
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double is IEEE 128-bit. Define __LONG_DOUBLE_IBM128__ if long
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double is IBM extended double.
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* config/rs6000/predicates.md (reg_or_indexed_operand): Allow
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SUBREGs.
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2015-10-29 Mikhail Maltsev <maltsevm@gmail.com>
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* genautomata.c: Use CHECKING_P instead of ENABLE_CHECKING.
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@ -684,7 +684,7 @@
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;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
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;; moves are supported.
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(define_predicate "reg_or_indexed_operand"
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(match_code "mem,reg")
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(match_code "mem,reg,subreg")
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{
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if (MEM_P (op))
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return indexed_or_indirect_operand (op, mode);
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@ -408,6 +408,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
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builtin_define ("__RSQRTE__");
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if (TARGET_FRSQRTES)
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builtin_define ("__RSQRTEF__");
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if (TARGET_FLOAT128)
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builtin_define ("__FLOAT128__");
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if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
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{
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@ -481,6 +483,11 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
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{
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builtin_define ("__LONG_DOUBLE_128__");
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builtin_define ("__LONGDOUBLE128");
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if (TARGET_IEEEQUAD)
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builtin_define ("__LONG_DOUBLE_IEEE128__");
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else
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builtin_define ("__LONG_DOUBLE_IBM128__");
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}
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switch (TARGET_CMODEL)
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@ -44,6 +44,7 @@
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#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
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| OPTION_MASK_POPCNTD \
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| OPTION_MASK_ALTIVEC \
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| OPTION_MASK_FLOAT128 \
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| OPTION_MASK_VSX \
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| OPTION_MASK_UPPER_REGS_DF)
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@ -80,6 +81,7 @@
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| OPTION_MASK_DIRECT_MOVE \
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| OPTION_MASK_DLMZB \
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| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
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| OPTION_MASK_FLOAT128 \
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| OPTION_MASK_FPRND \
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| OPTION_MASK_HTM \
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| OPTION_MASK_ISEL \
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@ -80,14 +80,6 @@ enum fpu_type_t
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};
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/* Float128 support. */
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enum float128_type_t
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{
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FLOAT128_UNSET = -1, /* Initial value. */
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FLOAT128_NONE, /* No __float128 support. */
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FLOAT128_SW /* software __float128 support. */
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};
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/* Types of costly dependences. */
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enum rs6000_dependence_cost
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{
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@ -1772,16 +1772,6 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
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&& IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
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&& ((regno & 1) == 0));
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/* If we don't allow 128-bit binary floating point, disallow the 128-bit
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types from going in any registers. Similarly if __float128 is not
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supported, don't allow __float128/__ibm128 types. */
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if (!TARGET_LONG_DOUBLE_128
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&& (mode == TFmode || mode == KFmode || mode == IFmode))
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return false;
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if (!TARGET_FLOAT128 && (mode == KFmode || mode == IFmode))
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return false;
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/* VSX registers that overlap the FPR registers are larger than for non-VSX
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implementations. Don't allow an item to be split between a FP register
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and an Altivec register. Allow TImode in all VSX registers if the user
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@ -2055,7 +2045,6 @@ rs6000_debug_reg_global (void)
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const char *trace_str;
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const char *abi_str;
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const char *cmodel_str;
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const char *float128_str;
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struct cl_target_option cl_opts;
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/* Modes we want tieable information on. */
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@ -2421,15 +2410,6 @@ rs6000_debug_reg_global (void)
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fprintf (stderr, DEBUG_FMT_S, "e500_double",
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(TARGET_E500_DOUBLE ? "true" : "false"));
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switch (TARGET_FLOAT128)
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{
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case FLOAT128_NONE: float128_str = "none"; break;
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case FLOAT128_SW: float128_str = "software"; break;
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default: float128_str = "unknown"; break;
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}
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fprintf (stderr, DEBUG_FMT_S, "float128", float128_str);
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if (TARGET_LINK_STACK)
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fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
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@ -2512,6 +2492,7 @@ rs6000_setup_reg_addr_masks (void)
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&& (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
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&& GET_MODE_SIZE (m2) <= 8
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&& !VECTOR_MODE_P (m2)
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&& !FLOAT128_VECTOR_P (m2)
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&& !COMPLEX_MODE_P (m2)
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&& !indexed_only_p
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&& !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8))
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@ -2657,6 +2638,20 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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align32 = 128;
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}
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/* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
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only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
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if (TARGET_FLOAT128)
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{
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rs6000_vector_mem[KFmode] = VECTOR_VSX;
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rs6000_vector_align[KFmode] = 128;
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if (FLOAT128_IEEE_P (TFmode))
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{
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rs6000_vector_mem[TFmode] = VECTOR_VSX;
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rs6000_vector_align[TFmode] = 128;
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}
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}
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/* V2DF mode, VSX only. */
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if (TARGET_VSX)
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{
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@ -2850,7 +2845,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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if (TARGET_FLOAT128)
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{
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rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
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if (rs6000_ieeequad)
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if (FLOAT128_IEEE_P (TFmode))
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rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
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}
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@ -2873,6 +2868,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
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reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
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reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
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reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
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reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
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reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
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reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
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reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
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@ -2880,6 +2877,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
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reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
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if (FLOAT128_IEEE_P (TFmode))
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{
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reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
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reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
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}
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/* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
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available. */
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if (TARGET_NO_SDMODE_STACK)
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@ -2933,6 +2936,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
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reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
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reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
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reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
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reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
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reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
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reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
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reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
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@ -2940,6 +2945,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
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reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
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if (FLOAT128_IEEE_P (TFmode))
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{
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reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
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reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
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}
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/* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
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available. */
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if (TARGET_NO_SDMODE_STACK)
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@ -3695,13 +3706,6 @@ rs6000_option_override_internal (bool global_init_p)
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&& optimize >= 3)
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rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
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/* Set the appropriate IEEE 128-bit floating option. Do not enable float128
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support by default until the libgcc support is added. */
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if (TARGET_FLOAT128 == FLOAT128_UNSET)
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TARGET_FLOAT128 = FLOAT128_NONE;
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else if (TARGET_FLOAT128 == FLOAT128_SW && !TARGET_VSX)
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error ("-mfloat128-software requires VSX support");
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/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
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support. If we only have ISA 2.06 support, and the user did not specify
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the switch, leave it set to -1 so the movmisalign patterns are enabled,
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@ -3741,6 +3745,15 @@ rs6000_option_override_internal (bool global_init_p)
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}
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}
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/* __float128 requires VSX support. */
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if (TARGET_FLOAT128 && !TARGET_VSX)
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{
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if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128) != 0)
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error ("-mfloat128 requires VSX support");
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rs6000_isa_flags &= ~OPTION_MASK_FLOAT128;
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}
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if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
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rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
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@ -3821,7 +3834,8 @@ rs6000_option_override_internal (bool global_init_p)
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unless the altivec ABI was set. This is set by default for 64-bit, but
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not for 32-bit. */
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if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
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rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
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rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
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| OPTION_MASK_FLOAT128)
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& ~rs6000_isa_flags_explicit);
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/* Enable Altivec ABI for AIX -maltivec. */
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@ -9427,6 +9441,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
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? CALL_LIBCALL : CALL_NORMAL);
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cum->sysv_gregno = GP_ARG_MIN_REG;
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cum->stdarg = stdarg_p (fntype);
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cum->libcall = libcall;
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cum->nargs_prototype = 0;
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if (incoming || cum->prototype)
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@ -10599,9 +10614,11 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
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rtx r, off;
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int i, k = 0;
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/* Do we also need to pass this argument in the parameter
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save area? */
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if (TARGET_64BIT && ! cum->prototype)
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/* Do we also need to pass this argument in the parameter save area?
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Library support functions for IEEE 128-bit are assumed to not need the
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value passed both in GPRs and in vector registers. */
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if (TARGET_64BIT && !cum->prototype
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&& (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
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{
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int align_words = ROUND_UP (cum->words, 2);
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k = rs6000_psave_function_arg (mode, type, align_words, rvec);
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@ -10832,11 +10849,14 @@ rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
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if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
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{
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/* If we are passing this arg in the fixed parameter save area
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(gprs or memory) as well as VRs, we do not use the partial
|
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bytes mechanism; instead, rs6000_function_arg will return a
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PARALLEL including a memory element as necessary. */
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if (TARGET_64BIT && ! cum->prototype)
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/* If we are passing this arg in the fixed parameter save area (gprs or
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memory) as well as VRs, we do not use the partial bytes mechanism;
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instead, rs6000_function_arg will return a PARALLEL including a memory
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element as necessary. Library support functions for IEEE 128-bit are
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assumed to not need the value passed both in GPRs and in vector
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registers. */
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if (TARGET_64BIT && !cum->prototype
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&& (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
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return 0;
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/* Otherwise, we pass in VRs only. Check for partial copies. */
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@ -14421,8 +14441,6 @@ rs6000_init_builtins (void)
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|||
tree tdecl;
|
||||
tree ftype;
|
||||
machine_mode mode;
|
||||
machine_mode ieee128_mode;
|
||||
machine_mode ibm128_mode;
|
||||
|
||||
if (TARGET_DEBUG_BUILTIN)
|
||||
fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
|
||||
|
|
@ -14495,26 +14513,24 @@ rs6000_init_builtins (void)
|
|||
TFmode will be either IEEE 128-bit floating point or the IBM double-double
|
||||
format that uses a pair of doubles, depending on the switches and
|
||||
defaults. */
|
||||
if (TARGET_IEEEQUAD)
|
||||
if (TARGET_FLOAT128)
|
||||
{
|
||||
ieee128_mode = TFmode;
|
||||
ibm128_mode = IFmode;
|
||||
}
|
||||
else
|
||||
{
|
||||
ieee128_mode = KFmode;
|
||||
ibm128_mode = TFmode;
|
||||
}
|
||||
ibm128_float_type_node = make_node (REAL_TYPE);
|
||||
TYPE_PRECISION (ibm128_float_type_node) = 128;
|
||||
layout_type (ibm128_float_type_node);
|
||||
SET_TYPE_MODE (ibm128_float_type_node, IFmode);
|
||||
|
||||
ieee128_float_type_node = make_node (REAL_TYPE);
|
||||
TYPE_PRECISION (ieee128_float_type_node) = 128;
|
||||
layout_type (ieee128_float_type_node);
|
||||
SET_TYPE_MODE (ieee128_float_type_node, ieee128_mode);
|
||||
ieee128_float_type_node = make_node (REAL_TYPE);
|
||||
TYPE_PRECISION (ieee128_float_type_node) = 128;
|
||||
layout_type (ieee128_float_type_node);
|
||||
SET_TYPE_MODE (ieee128_float_type_node, KFmode);
|
||||
|
||||
ibm128_float_type_node = make_node (REAL_TYPE);
|
||||
TYPE_PRECISION (ibm128_float_type_node) = 128;
|
||||
layout_type (ibm128_float_type_node);
|
||||
SET_TYPE_MODE (ibm128_float_type_node, ibm128_mode);
|
||||
lang_hooks.types.register_builtin_type (ieee128_float_type_node,
|
||||
"__float128");
|
||||
|
||||
lang_hooks.types.register_builtin_type (ibm128_float_type_node,
|
||||
"__ibm128");
|
||||
}
|
||||
|
||||
/* Initialize the modes for builtin_function_type, mapping a machine mode to
|
||||
tree type node. */
|
||||
|
|
@ -33093,8 +33109,8 @@ rs6000_scalar_mode_supported_p (machine_mode mode)
|
|||
|
||||
if (DECIMAL_FLOAT_MODE_P (mode))
|
||||
return default_decimal_float_supported_p ();
|
||||
else if (mode == KFmode)
|
||||
return TARGET_FLOAT128;
|
||||
else if (TARGET_FLOAT128 && (mode == KFmode || mode == IFmode))
|
||||
return true;
|
||||
else
|
||||
return default_scalar_mode_supported_p (mode);
|
||||
}
|
||||
|
|
@ -33205,6 +33221,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
|
|||
{ "dlmzb", OPTION_MASK_DLMZB, false, true },
|
||||
{ "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
|
||||
false, true },
|
||||
{ "float128", OPTION_MASK_FLOAT128, false, true },
|
||||
{ "fprnd", OPTION_MASK_FPRND, false, true },
|
||||
{ "hard-dfp", OPTION_MASK_DFP, false, true },
|
||||
{ "htm", OPTION_MASK_HTM, false, true },
|
||||
|
|
@ -33283,7 +33300,7 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
|
|||
struct rs6000_opt_var {
|
||||
const char *name; /* option name */
|
||||
size_t global_offset; /* offset of the option in global_options. */
|
||||
size_t target_offset; /* offset of the option in target optiosn. */
|
||||
size_t target_offset; /* offset of the option in target options. */
|
||||
};
|
||||
|
||||
static struct rs6000_opt_var const rs6000_opt_vars[] =
|
||||
|
|
|
|||
|
|
@ -1217,11 +1217,16 @@ enum data_align { align_abi, align_opt, align_both };
|
|||
((MODE) == V4SFmode \
|
||||
|| (MODE) == V2DFmode) \
|
||||
|
||||
#define ALTIVEC_VECTOR_MODE(MODE) \
|
||||
((MODE) == V16QImode \
|
||||
|| (MODE) == V8HImode \
|
||||
|| (MODE) == V4SFmode \
|
||||
|| (MODE) == V4SImode)
|
||||
/* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
|
||||
really a vector, but we want to treat it as a vector for moves, and
|
||||
such. */
|
||||
|
||||
#define ALTIVEC_VECTOR_MODE(MODE) \
|
||||
((MODE) == V16QImode \
|
||||
|| (MODE) == V8HImode \
|
||||
|| (MODE) == V4SFmode \
|
||||
|| (MODE) == V4SImode \
|
||||
|| FLOAT128_VECTOR_P (MODE))
|
||||
|
||||
#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
|
||||
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|
||||
|
|
@ -1248,12 +1253,19 @@ enum data_align { align_abi, align_opt, align_both };
|
|||
|
||||
PTImode cannot tie with other modes because PTImode is restricted to even
|
||||
GPR registers, and TImode can go in any GPR as well as VSX registers (PR
|
||||
57744). */
|
||||
57744).
|
||||
|
||||
Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
|
||||
128-bit floating point on VSX systems ties with other vectors. */
|
||||
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
||||
((MODE1) == PTImode \
|
||||
? (MODE2) == PTImode \
|
||||
: (MODE2) == PTImode \
|
||||
? 0 \
|
||||
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
|
||||
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
|
||||
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
|
||||
? 0 \
|
||||
: SCALAR_FLOAT_MODE_P (MODE1) \
|
||||
? SCALAR_FLOAT_MODE_P (MODE2) \
|
||||
: SCALAR_FLOAT_MODE_P (MODE2) \
|
||||
|
|
@ -1266,10 +1278,6 @@ enum data_align { align_abi, align_opt, align_both };
|
|||
? SPE_VECTOR_MODE (MODE2) \
|
||||
: SPE_VECTOR_MODE (MODE2) \
|
||||
? 0 \
|
||||
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
|
||||
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
|
||||
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
|
||||
? 0 \
|
||||
: 1)
|
||||
|
||||
/* Post-reload, we can't use any new AltiVec registers, as we already
|
||||
|
|
@ -1801,6 +1809,7 @@ typedef struct rs6000_args
|
|||
GPR space (darwin64) */
|
||||
int named; /* false for varargs params */
|
||||
int escapes; /* if function visible outside tu */
|
||||
int libcall; /* If this is a compiler generated call. */
|
||||
} CUMULATIVE_ARGS;
|
||||
|
||||
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
||||
|
|
|
|||
|
|
@ -601,18 +601,6 @@ moptimize-swaps
|
|||
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
|
||||
Analyze and remove doubleword swaps from VSX computations.
|
||||
|
||||
mfloat128-
|
||||
Target RejectNegative Joined Enum(float128_type_t) Var(TARGET_FLOAT128) Init(FLOAT128_UNSET) Save
|
||||
-mfloat128-{software,none} - Specify how IEEE 128-bit floating point is used.
|
||||
|
||||
Enum
|
||||
Name(float128_type_t) Type(enum float128_type_t)
|
||||
|
||||
EnumValue
|
||||
Enum(float128_type_t) String(none) Value(FLOAT128_NONE)
|
||||
|
||||
EnumValue
|
||||
Enum(float128_type_t) String(software) Value(FLOAT128_SW)
|
||||
|
||||
EnumValue
|
||||
Enum(float128_type_t) String(sw) Value(FLOAT128_SW)
|
||||
mfloat128
|
||||
Target Report Mask(FLOAT128) Var(rs6000_isa_flags)
|
||||
Enable/disable IEEE 128-bit floating point via the __float128 keyword.
|
||||
|
|
|
|||
Loading…
Reference in New Issue