(HARD_REGNO_MODE_OK): Allow DImode in FP registers.
(CONDITIONAL_REGISTER_USAGE): Delete ppcas mention from comment. (RTX_COSTS): Costs based upon processor_type enum. From-SVN: r6818
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@ -399,13 +399,16 @@ extern char *rs6000_cpu_string;
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On RS/6000, the cpu registers can hold any mode but the float registers
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can hold only floating modes and CR register can only hold CC modes. We
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cannot put DImode or TImode anywhere except general register and they
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must be able to fit within the register set. */
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For POWER and PowerPC, the GPRs can hold any mode, but the float
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registers only can hold floating modes and DImode, and CR register only
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can hold CC modes. We cannot put TImode anywhere except general
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register and it must be able to fit within the register set. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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(FP_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_FLOAT \
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(FP_REGNO_P (REGNO) ? \
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(GET_MODE_CLASS (MODE) == MODE_FLOAT \
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|| (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD)) \
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: CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
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: ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
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@ -465,8 +468,7 @@ extern char *rs6000_cpu_string;
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/* Define this macro to change register usage conditional on target flags.
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Set MQ register fixed (already call_used) if not POWER architecture
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(RIOS1, RIOS2, and PPC601) so that it will not be allocated.
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Provide alternate register names for ppcas assembler */
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(RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. */
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#define CONDITIONAL_REGISTER_USAGE \
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if (!TARGET_POWER) \
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@ -1402,10 +1404,21 @@ struct rs6000_args {int words, fregno, nargs_prototype; };
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#define RTX_COSTS(X,CODE,OUTER_CODE) \
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case MULT: \
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switch (rs6000_cpu) \
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{ \
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case PROCESSOR_RIOS1: \
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return (GET_CODE (XEXP (X, 1)) != CONST_INT \
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? COSTS_N_INSNS (5) \
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: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
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? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
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case PROCESSOR_RIOS2: \
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return COSTS_N_INSNS (2); \
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case PROCESSOR_PPC601: \
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case PROCESSOR_PPC603: \
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case PROCESSOR_PPC604: \
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case PROCESSOR_PPC620: \
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return COSTS_N_INSNS (5); \
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} \
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case DIV: \
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case MOD: \
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if (GET_CODE (XEXP (X, 1)) == CONST_INT \
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@ -1414,7 +1427,18 @@ struct rs6000_args {int words, fregno, nargs_prototype; };
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/* otherwise fall through to normal divide. */ \
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case UDIV: \
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case UMOD: \
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switch (rs6000_cpu) \
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{ \
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case PROCESSOR_RIOS1: \
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return COSTS_N_INSNS (19); \
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case PROCESSOR_RIOS2: \
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return COSTS_N_INSNS (13); \
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case PROCESSOR_PPC601: \
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case PROCESSOR_PPC603: \
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case PROCESSOR_PPC604: \
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case PROCESSOR_PPC620: \
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return COSTS_N_INSNS (36); \
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} \
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case MEM: \
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/* MEM should be slightly more expensive than (plus (reg) (const)) */ \
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return 5;
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