2003-04-02 Vladimir Makarov <vmakarov@redhat.com>
* config/rs6000/rs6000.c (TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Redefine the macros. (rs6000_issue_rate): Add case for 8540. (rs6000_use_sched_lookahead): New function. * config/rs6000/8540.md: Rename SIU units into SU ones and MIU units into MU ones. (ppc8540_branch, ppc8540_cr_logical): Add one cycle in the reservation before retirement. (ppc8540_multiply, ppc8540_load, ppc8540_store, ppc8540_simple_float, ppc8540_vector_load, ppc8540_vector_store): Remove additional cycle in the reservation before retirement. (ppc8540_mfcr, ppc8540_mtcrf, ppc8540_mtjmpr): Add missed reservation of ppc8540_issue. From-SVN: r65167
This commit is contained in:
Vladimir Makarov
Vladimir Makarov
parent
0f91f09492
commit
be12c2b0cc
@ -1,3 +1,21 @@
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2003-04-02 Vladimir Makarov <vmakarov@redhat.com>
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* config/rs6000/rs6000.c
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(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Redefine the
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macros.
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(rs6000_issue_rate): Add case for 8540.
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(rs6000_use_sched_lookahead): New function.
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* config/rs6000/8540.md: Rename SIU units into SU ones and MIU
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units into MU ones.
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(ppc8540_branch, ppc8540_cr_logical): Add one cycle in the
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reservation before retirement.
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(ppc8540_multiply, ppc8540_load, ppc8540_store,
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ppc8540_simple_float, ppc8540_vector_load, ppc8540_vector_store):
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Remove additional cycle in the reservation before retirement.
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(ppc8540_mfcr, ppc8540_mtcrf, ppc8540_mtjmpr): Add missed
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reservation of ppc8540_issue.
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2003-04-02 Andreas Schwab <schwab@suse.de>
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* real.c (decode_ieee_single): Fix decoding of SNaN bit.
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@ -20,6 +20,13 @@
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(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
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(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
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;; We don't simulate general issue queue (GIC). If we have SU insn
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;; and then SU1 insn, they can not be issued on the same cycle
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;; (although SU1 insn and then SU insn can be issued) because the SU
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;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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;; multipass insn scheduling will find the situation and issue the SU1
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;; insn and then the SU insn.
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(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
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;; We could describe completion buffers slots in combination with the
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@ -37,19 +44,19 @@
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;; Branch unit:
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(define_cpu_unit "ppc8540_bu" "ppc8540_most")
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;; SIU:
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(define_cpu_unit "ppc8540_siu0_stage0,ppc8540_siu1_stage0" "ppc8540_most")
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;; SU:
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(define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
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;; We could describe here MIU subunits for float multiply, float add
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;; We could describe here MU subunits for float multiply, float add
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;; etc. But the result automaton would behave the same way as the
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;; described one pipeline below because MIU can start only one insn
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;; described one pipeline below because MU can start only one insn
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;; per cycle. Actually we could simplify the automaton more not
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;; describing stages 1-3, the result automata would be the same.
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(define_cpu_unit "ppc8540_miu_stage0,ppc8540_miu_stage1" "ppc8540_most")
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(define_cpu_unit "ppc8540_miu_stage2,ppc8540_miu_stage3" "ppc8540_most")
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(define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
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(define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
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;; The following unit is used to describe non-pipelined division.
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(define_cpu_unit "ppc8540_miu_div" "ppc8540_long")
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(define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
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;; Here we simplified LSU unit description not describing the stages.
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(define_cpu_unit "ppc8540_lsu" "ppc8540_most")
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@ -58,13 +65,13 @@
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(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
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(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
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(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
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(define_cpu_unit "present_ppc8540_siu0_stage0" "ppc8540_most")
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(define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
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(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
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(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
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(presence_set "present_ppc8540_siu0_stage0" "ppc8540_siu0_stage0")
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(presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
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;; Some useful abbreviations.
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(define_reservation "ppc8540_decode"
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@ -73,153 +80,156 @@
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"ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
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(define_reservation "ppc8540_retire"
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"ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
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(define_reservation "ppc8540_siu_stage0"
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"ppc8540_siu0_stage0|ppc8540_siu1_stage0+present_ppc8540_siu0_stage0")
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(define_reservation "ppc8540_su_stage0"
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"ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
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;; Simple SIU insns
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(define_insn_reservation "ppc8540_siu" 1
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;; Simple SU insns
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(define_insn_reservation "ppc8540_su" 1
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(and (eq_attr "type" "integer,cmp,compare,delayed_compare,fast_compare")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Branch. Actually this latency time is not used by the scheduler.
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(define_insn_reservation "ppc8540_branch" 1
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(and (eq_attr "type" "jmpreg,branch")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_bu+ppc8540_retire")
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Multiply
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(define_insn_reservation "ppc8540_multiply" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
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ppc8540_miu_stage2,ppc8540_miu_stage3,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Divide. We use the average latency time here. We omit reserving a
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;; retire unit because of the result automata will be huge.
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;; retire unit because of the result automata will be huge. We ignore
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;; reservation of miu_stage3 here because we use the average latency
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;; time.
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(define_insn_reservation "ppc8540_divide" 14
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
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ppc8540_miu_div*13")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; CR logical
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(define_insn_reservation "ppc8540_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_bu+ppc8540_retire")
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Mfcr
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(define_insn_reservation "ppc8540_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtcrf
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(define_insn_reservation "ppc8540_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtjmpr
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(define_insn_reservation "ppc8540_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_siu_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Loads
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(define_insn_reservation "ppc8540_load" 3
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Stores.
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(define_insn_reservation "ppc8540_store" 3
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(and (eq_attr "type" "store,store_ux,store_u")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Simple FP
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(define_insn_reservation "ppc8540_simple_float" 1
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(and (eq_attr "type" "fpsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; FP
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(define_insn_reservation "ppc8540_float" 4
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
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ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; float divides. We omit reserving a retire unit because of the
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;; result automata will be huge.
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;; float divides. We omit reserving a retire unit and miu_stage3
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;; because of the result automata will be huge.
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(define_insn_reservation "ppc8540_float_vector_divide" 29
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(and (eq_attr "type" "vecfdiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
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ppc8540_miu_div*28")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*28")
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;; Brinc
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(define_insn_reservation "ppc8540_brinc" 1
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(and (eq_attr "type" "brinc")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Simple vector
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(define_insn_reservation "ppc8540_simple_vector" 1
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(and (eq_attr "type" "vecsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Simple vector compare
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(define_insn_reservation "ppc8540_simple_vector_compare" 1
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(and (eq_attr "type" "veccmpsimple")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Vector compare
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(define_insn_reservation "ppc8540_vector_compare" 1
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(and (eq_attr "type" "veccmp")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; evsplatfi evsplati
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(define_insn_reservation "ppc8540_vector_perm" 1
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(and (eq_attr "type" "vecperm")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Vector float
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(define_insn_reservation "ppc8540_float_vector" 4
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(and (eq_attr "type" "vecfloat")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
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ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Vector divides: Use the average. We omit reserving a retire unit
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;; because of the result automata will be huge.
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;; because of the result automata will be huge. We ignore reservation
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;; of miu_stage3 here because we use the average latency time.
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(define_insn_reservation "ppc8540_vector_divide" 14
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(and (eq_attr "type" "vecdiv")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
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ppc8540_miu_div*13")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; Complex vector.
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(define_insn_reservation "ppc8540_complex_vector" 4
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(and (eq_attr "type" "veccomplex")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
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ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Vector load
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(define_insn_reservation "ppc8540_vector_load" 3
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Vector store
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(define_insn_reservation "ppc8540_vector_store" 3
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "ppc8540"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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@ -241,6 +241,7 @@ static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *));
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static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
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static int rs6000_adjust_priority PARAMS ((rtx, int));
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static int rs6000_issue_rate PARAMS ((void));
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static int rs6000_use_sched_lookahead PARAMS ((void));
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static void rs6000_init_builtins PARAMS ((void));
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static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
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@ -407,6 +408,9 @@ static const char alt_reg_names[][8] =
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#undef TARGET_SCHED_ADJUST_PRIORITY
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#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
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#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
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#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
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#undef TARGET_INIT_BUILTINS
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#define TARGET_INIT_BUILTINS rs6000_init_builtins
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@ -12661,6 +12665,7 @@ rs6000_issue_rate ()
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case CPU_PPC603:
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case CPU_PPC750:
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case CPU_PPC7400:
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case CPU_PPC8540:
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return 2;
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case CPU_RIOS2:
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case CPU_PPC604:
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@ -12674,6 +12679,17 @@ rs6000_issue_rate ()
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}
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}
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/* Return how many instructions to look ahead for better insn
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scheduling. */
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static int
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rs6000_use_sched_lookahead ()
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{
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if (rs6000_cpu_attr == CPU_PPC8540)
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return 4;
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return 0;
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}
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/* Length in units of the trampoline for entering a nested function. */
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user