[PR99581] Use relaxed memory for more aarch64 memory constraints
The original patch for PR99581 resulted in GCC testsuite regression as some constraints were not declared as relaxed memory ones. This patch fixes this. gcc/ChangeLog: PR target/99581 * config/aarch64/constraints.md (Utq, UOb, UOh, UOw, UOd, UOty): Use define_relaxed_memory_constraint for them.
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@ -323,7 +323,7 @@
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(and (match_code "mem")
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(match_test "aarch64_simd_mem_operand_p (op)")))
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(define_memory_constraint "Utq"
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(define_relaxed_memory_constraint "Utq"
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"@internal
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An address valid for loading or storing a 128-bit AdvSIMD register"
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(and (match_code "mem")
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@ -336,32 +336,32 @@
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(and (match_code "mem")
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(match_test "aarch64_sve_ld1rq_operand_p (op)")))
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(define_memory_constraint "UOb"
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(define_relaxed_memory_constraint "UOb"
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"@internal
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An address valid for SVE LD1ROH."
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(and (match_code "mem")
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(match_test "aarch64_sve_ld1ro_operand_p (op, QImode)")))
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(define_memory_constraint "UOh"
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(define_relaxed_memory_constraint "UOh"
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"@internal
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An address valid for SVE LD1ROH."
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(and (match_code "mem")
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(match_test "aarch64_sve_ld1ro_operand_p (op, HImode)")))
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(define_memory_constraint "UOw"
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(define_relaxed_memory_constraint "UOw"
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"@internal
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An address valid for SVE LD1ROW."
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(and (match_code "mem")
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(match_test "aarch64_sve_ld1ro_operand_p (op, SImode)")))
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(define_memory_constraint "UOd"
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(define_relaxed_memory_constraint "UOd"
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"@internal
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An address valid for SVE LD1ROD."
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(and (match_code "mem")
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(match_test "aarch64_sve_ld1ro_operand_p (op, DImode)")))
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(define_memory_constraint "Uty"
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(define_relaxed_memory_constraint "Uty"
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"@internal
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An address valid for SVE LD1Rs."
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(and (match_code "mem")
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