sse.md (*mov<mode>_internal): Merge with *mov<mode>_internal_rex64.
* config/i386/sse.md (*mov<mode>_internal): Merge with *mov<mode>_internal_rex64. Use x64 and nox64 isa attributes. Emit insn template depending on type attribute. Use HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require movd instead of movq mnemonic for interunit moves. Rewrite mode attribute calculation. Remove unit attribute calculation. Set prefix attribute to maybe_vex for sselog1 and ssemov types. Set prefix_data16 attribute for DImode ssemov types. Use Ym instead of y for SSE-MMX conversion alternatives. Reorder operand constraints. testsuite/ChangeLog: * gcc.target/i386/pr22152.c (dg-options): Add -mtune=core2. From-SVN: r196981
This commit is contained in:
Uros Bizjak
parent
1e8a79379d
commit
bed852cf7a
@ -1,3 +1,16 @@
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2013-03-22 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (*mov<mode>_internal): Merge with
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*mov<mode>_internal_rex64. Use x64 and nox64 isa attributes.
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Emit insn template depending on type attribute. Use
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HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require
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movd instead of movq mnemonic for interunit moves. Rewrite mode
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attribute calculation. Remove unit attribute calculation.
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Set prefix attribute to maybe_vex for sselog1 and ssemov types.
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Set prefix_data16 attribute for DImode ssemov types.
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Use Ym instead of y for SSE-MMX conversion alternatives.
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Reorder operand constraints.
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2013-03-22 Steven Bosscher <steven@gcc.gnu.org>
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* df.h (df_insn_delete): Adjust prototype.
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@ -31,7 +44,7 @@
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2013-03-22 Richard Biener <rguenther@suse.de>
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* is-a.h (as_a): Use gcc_checking_assert.
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2013-03-22 Ian Bolton <ian.bolton@arm.com>
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* config/aarch64/aarch64.c (aarch64_print_operand): New
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@ -47,8 +60,7 @@
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(create_vop_ref_mapping_loop): Remove.
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(create_vop_ref_mapping): Likewise.
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(analyze_memory_references): Initialize refs_stored_in_loop.
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(LOOP_DEP_BIT): New define to map to bits in (in)dep_loop
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bitmaps.
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(LOOP_DEP_BIT): New define to map to bits in (in)dep_loop bitmaps.
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(record_indep_loop): Remove.
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(record_dep_loop): New function.
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(ref_indep_loop_p_1): Adjust to only walk over references
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@ -76,128 +76,126 @@
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DONE;
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})
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;; movd instead of movq is required to handle broken assemblers.
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(define_insn "*mov<mode>_internal_rex64"
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[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
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"=rm,r,!?y,!y,!?y,m ,!y ,*x,x,x ,m,r ,Yi")
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(match_operand:MMXMODEI8 1 "vector_move_operand"
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"Cr ,m,C ,!y,m ,!?y,*x,!y ,C,xm,x,Yi,r"))]
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"TARGET_64BIT && TARGET_MMX
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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mov{q}\t{%1, %0|%0, %1}
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mov{q}\t{%1, %0|%0, %1}
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pxor\t%0, %0
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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movdq2q\t{%1, %0|%0, %1}
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movq2dq\t{%1, %0|%0, %1}
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%vpxor\t%0, %d0
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%vmovq\t{%1, %0|%0, %1}
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%vmovq\t{%1, %0|%0, %1}
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%vmovd\t{%1, %0|%0, %1}
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%vmovd\t{%1, %0|%0, %1}"
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[(set (attr "type")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "imov")
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(eq_attr "alternative" "2")
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(const_string "mmx")
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(eq_attr "alternative" "3,4,5")
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(const_string "mmxmov")
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(eq_attr "alternative" "6,7")
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(const_string "ssecvt")
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(eq_attr "alternative" "8")
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(const_string "sselog1")
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]
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(const_string "ssemov")))
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(set (attr "unit")
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(if_then_else (eq_attr "alternative" "6,7")
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(const_string "mmx")
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(const_string "*")))
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(set (attr "prefix_rep")
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(if_then_else (eq_attr "alternative" "6,7,9")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_data16")
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(if_then_else (eq_attr "alternative" "10,11,12")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_rex")
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(if_then_else (eq_attr "alternative" "9,10")
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(symbol_ref "x86_extended_reg_mentioned_p (insn)")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "8,9,10,11,12")
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(const_string "maybe_vex")
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(const_string "orig")))
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(set_attr "mode" "DI")])
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(define_insn "*mov<mode>_internal"
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[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
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"=!?y,!y,!?y,m ,!y,*x,*x,*x ,m ,*x,*x,*x,m ,r ,m")
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"=r ,o ,r,r ,m ,!?y,!y,!?y,m ,x,x,x,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
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(match_operand:MMXMODEI8 1 "vector_move_operand"
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"C ,!y,m ,!?y,*x,!y,C ,*xm,*x,C ,*x,m ,*x,irm,r"))]
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"!TARGET_64BIT && TARGET_MMX
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"rCo,rC,C,rm,rC,C ,!y,m ,!?y,C,x,m,x,C ,*x,m ,*x,Yi,r ,*Yi,!Ym"))]
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"TARGET_MMX
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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pxor\t%0, %0
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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movdq2q\t{%1, %0|%0, %1}
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movq2dq\t{%1, %0|%0, %1}
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%vpxor\t%0, %d0
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%vmovq\t{%1, %0|%0, %1}
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%vmovq\t{%1, %0|%0, %1}
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xorps\t%0, %0
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movaps\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}
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#
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#"
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{
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switch (get_attr_type (insn))
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{
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case TYPE_MULTI:
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return "#";
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case TYPE_IMOV:
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if (get_attr_mode (insn) == MODE_SI)
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return "mov{l}\t{%1, %k0|%k0, %1}";
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else
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return "mov{q}\t{%1, %0|%0, %1}";
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case TYPE_MMX:
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return "pxor\t%0, %0";
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case TYPE_MMXMOV:
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#ifndef HAVE_AS_IX86_INTERUNIT_MOVQ
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/* Handle broken assemblers that require movd instead of movq. */
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if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
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return "movd\t{%1, %0|%0, %1}";
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#endif
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return "movq\t{%1, %0|%0, %1}";
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case TYPE_SSECVT:
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if (SSE_REG_P (operands[0]))
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return "movq2dq\t{%1, %0|%0, %1}";
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else
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return "movdq2q\t{%1, %0|%0, %1}";
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case TYPE_SSEMOV:
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switch (get_attr_mode (insn))
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{
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case MODE_DI:
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#ifndef HAVE_AS_IX86_INTERUNIT_MOVQ
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/* Handle broken assemblers that require movd instead of movq. */
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if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
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return "%vmovd\t{%1, %0|%0, %1}";
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#endif
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return "%vmovq\t{%1, %0|%0, %1}";
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case MODE_TI:
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V2SF:
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gcc_assert (!TARGET_AVX);
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return "movlps\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "4,5,6,7,8")
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(const_string "sse2")
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(eq_attr "alternative" "9,10,11,12")
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(const_string "noavx")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "nox64")
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(eq_attr "alternative" "2,3,4,9,10,11,12,17,18")
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(const_string "x64")
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]
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(const_string "*")))
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(const_string "*")))
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(set (attr "type")
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(cond [(eq_attr "alternative" "0")
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(const_string "mmx")
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(eq_attr "alternative" "1,2,3")
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(const_string "mmxmov")
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(eq_attr "alternative" "4,5")
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(const_string "ssecvt")
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(eq_attr "alternative" "6,9")
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(const_string "sselog1")
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(eq_attr "alternative" "13,14")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "multi")
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(eq_attr "alternative" "2,3,4")
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(const_string "imov")
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(eq_attr "alternative" "5")
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(const_string "mmx")
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(eq_attr "alternative" "6,7,8")
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(const_string "mmxmov")
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(eq_attr "alternative" "9,13")
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(const_string "sselog1")
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(eq_attr "alternative" "19,20")
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(const_string "ssecvt")
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]
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(const_string "ssemov")))
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(set (attr "unit")
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(if_then_else (eq_attr "alternative" "4,5")
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(const_string "mmx")
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(const_string "*")))
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(set (attr "prefix_rep")
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(if_then_else
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(ior (eq_attr "alternative" "4,5")
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(and (eq_attr "alternative" "7")
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(not (match_test "TARGET_AVX"))))
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_data16")
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(if_then_else
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(and (eq_attr "alternative" "8")
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(not (match_test "TARGET_AVX")))
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(set (attr "prefix_rex")
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(if_then_else (eq_attr "alternative" "17,18")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "6,7,8")
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(if_then_else (eq_attr "type" "sselog1,ssemov")
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(const_string "maybe_vex")
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(const_string "orig")))
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(set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
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(set (attr "prefix_data16")
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(if_then_else
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(and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
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(const_string "1")
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(const_string "*")))
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(set (attr "mode")
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(cond [(eq_attr "alternative" "2")
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(const_string "SI")
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(eq_attr "alternative" "9,10,13,14")
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(cond [(ior (not (match_test "TARGET_SSE2"))
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
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(match_test "optimize_function_for_size_p (cfun)")
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(const_string "V4SF")
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]
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(const_string "TI"))
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(and (eq_attr "alternative" "11,12,15,16")
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(not (match_test "TARGET_SSE2")))
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(const_string "V2SF")
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]
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(const_string "DI")))])
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(define_expand "movv2sf"
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[(set (match_operand:V2SF 0 "nonimmediate_operand")
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@ -1,3 +1,7 @@
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2013-03-22 Uros Bizjak <ubizjak@gmail.com>
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* gcc.target/i386/pr22152.c (dg-options): Add -mtune=core2.
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2013-03-22 Sebastian Huber <sebastian.huber@embedded-brains.de>
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PR testsuite/55994
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -msse2" } */
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/* { dg-options "-O2 -msse2 -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */
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/* { dg-options "-O2 -msse2 -mtune=core2" } */
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/* { dg-additional-options "-mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */
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/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
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#include <mmintrin.h>
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