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re PR target/33393 (floatsisf2_sse_vector_nointernunit doesn't work on 32bit)

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PR target/33393
	* i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for
	!SSE_MATH

From-SVN: r128414
This commit is contained in:
Jan Hubicka 2007-09-12 09:02:31 +02:00 committed by Jan Hubicka
parent 926e663ef1
commit bf019a1f7f
2 changed files with 14 additions and 5 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2007-09-12 Jan Hubicka <jh@suse.cz>
PR target/33393
* i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for
!SSE_MATH
2007-09-12 Christian Bruel <christian.bruel@st.com> 2007-09-12 Christian Bruel <christian.bruel@st.com>
* sh.h (SH_DBX_REGISTER_NUMBER): Added fpscr, fixed sr/gbr regs. * sh.h (SH_DBX_REGISTER_NUMBER): Added fpscr, fixed sr/gbr regs.
* linux-unwind.h (SH_DWARF_FRAME_GBR): fixed. * linux-unwind.h (SH_DWARF_FRAME_GBR): fixed.

13
gcc/config/i386/i386.md
View File

@ -3927,7 +3927,7 @@
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
(float_extend:DF (float_extend:DF
(match_operand:SF 1 "nonimmediate_operand" "")))] (match_operand:SF 1 "nonimmediate_operand" "")))]
"TARGET_USE_VECTOR_CONVERTS && !optimize_size "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
&& reload_completed && SSE_REG_P (operands[0])" && reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 2) [(set (match_dup 2)
(float_extend:V2DF (float_extend:V2DF
@ -4063,7 +4063,7 @@
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "")))] (match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_USE_VECTOR_CONVERTS && !optimize_size "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
&& reload_completed && SSE_REG_P (operands[0])" && reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 2) [(set (match_dup 2)
(vec_concat:V4SF (vec_concat:V4SF
@ -4876,7 +4876,8 @@
(define_insn "*floatsisf2_sse_vector_nointernunit" (define_insn "*floatsisf2_sse_vector_nointernunit"
[(set (match_operand:SF 0 "register_operand" "=x") [(set (match_operand:SF 0 "register_operand" "=x")
(float:SF (match_operand:SI 1 "memory_operand" "m")))] (float:SF (match_operand:SI 1 "memory_operand" "m")))]
"flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size "TARGET_SSE_MATH && flag_trapping_math
&& TARGET_USE_VECTOR_CONVERTS && !optimize_size
&& !TARGET_INTER_UNIT_MOVES" && !TARGET_INTER_UNIT_MOVES"
"#" "#"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
@ -4884,7 +4885,8 @@
(define_insn "*floatsisf2_sse_vector_internunit" (define_insn "*floatsisf2_sse_vector_internunit"
[(set (match_operand:SF 0 "register_operand" "=x,x") [(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))] (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))]
"flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size "TARGET_SSE_MATH && flag_trapping_math
&& TARGET_USE_VECTOR_CONVERTS && !optimize_size
&& TARGET_INTER_UNIT_MOVES" && TARGET_INTER_UNIT_MOVES"
"#" "#"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
@ -4921,7 +4923,8 @@
(define_insn "*floatsisf2_sse_vector" (define_insn "*floatsisf2_sse_vector"
[(set (match_operand:SF 0 "register_operand" "=x") [(set (match_operand:SF 0 "register_operand" "=x")
(float:SF (match_operand:SI 1 "register_operand" "x")))] (float:SF (match_operand:SI 1 "register_operand" "x")))]
"!flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size "TARGET_SSE_MATH && !flag_trapping_math
&& TARGET_USE_VECTOR_CONVERTS && !optimize_size
&& !TARGET_INTER_UNIT_MOVES" && !TARGET_INTER_UNIT_MOVES"
"cvtdq2ps\t{%1, %0|%0, %1}" "cvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")