[AArch64] Use SVE FABD in conditional arithmetic
This patch extends the FABD support so that it handles conditional arithmetic. We're relying on combine for this, since there's no associated IFN_COND_* (yet?). 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org> gcc/ * config/aarch64/aarch64-sve.md (*aarch64_cond_abd<SVE_F:mode>_2) (*aarch64_cond_abd<SVE_F:mode>_3) (*aarch64_cond_abd<SVE_F:mode>_any): New patterns. gcc/testsuite/ * gcc.target/aarch64/sve/cond_fabd_1.c: New test. * gcc.target/aarch64/sve/cond_fabd_1_run.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_2.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_2_run.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_3.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_3_run.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_4.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_4_run.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_5.c: Likewise. * gcc.target/aarch64/sve/cond_fabd_5_run.c: Likewise. Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org> From-SVN: r274507
This commit is contained in:
parent
9730c5ccd5
commit
bf30864e4c
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@ -1,3 +1,10 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* config/aarch64/aarch64-sve.md (*aarch64_cond_abd<SVE_F:mode>_2)
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(*aarch64_cond_abd<SVE_F:mode>_3)
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(*aarch64_cond_abd<SVE_F:mode>_any): New patterns.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -2795,6 +2795,123 @@
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}
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)
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;; Predicated floating-point absolute difference, merging with the first
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;; input.
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(define_insn_and_rewrite "*aarch64_cond_abd<mode>_2"
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[(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(unspec:SVE_F
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[(match_operand 4)
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(match_operand:SI 5 "aarch64_sve_gp_strictness")
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(unspec:SVE_F
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[(match_operand 6)
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(match_operand:SI 7 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "0, w")
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(match_operand:SVE_F 3 "register_operand" "w, w")]
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UNSPEC_COND_FSUB)]
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UNSPEC_COND_FABS)
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& aarch64_sve_pred_dominates_p (&operands[4], operands[1])
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&& aarch64_sve_pred_dominates_p (&operands[6], operands[1])"
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"@
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fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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"&& (!rtx_equal_p (operands[1], operands[4])
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|| !rtx_equal_p (operands[1], operands[6]))"
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{
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operands[4] = copy_rtx (operands[1]);
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operands[6] = copy_rtx (operands[1]);
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}
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated floating-point absolute difference, merging with the second
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;; input.
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(define_insn_and_rewrite "*aarch64_cond_abd<mode>_3"
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[(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(unspec:SVE_F
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[(match_operand 4)
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(match_operand:SI 5 "aarch64_sve_gp_strictness")
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(unspec:SVE_F
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[(match_operand 6)
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(match_operand:SI 7 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "w, w")
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(match_operand:SVE_F 3 "register_operand" "0, w")]
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UNSPEC_COND_FSUB)]
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UNSPEC_COND_FABS)
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(match_dup 3)]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& aarch64_sve_pred_dominates_p (&operands[4], operands[1])
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&& aarch64_sve_pred_dominates_p (&operands[6], operands[1])"
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"@
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fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
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movprfx\t%0, %3\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>"
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"&& (!rtx_equal_p (operands[1], operands[4])
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|| !rtx_equal_p (operands[1], operands[6]))"
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{
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operands[4] = copy_rtx (operands[1]);
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operands[6] = copy_rtx (operands[1]);
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}
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated floating-point absolute difference, merging with an
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;; independent value.
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(define_insn_and_rewrite "*aarch64_cond_abd<mode>_any"
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[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl")
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(unspec:SVE_F
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[(match_operand 5)
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(match_operand:SI 6 "aarch64_sve_gp_strictness")
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(unspec:SVE_F
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[(match_operand 7)
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(match_operand:SI 8 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "0, w, w, w, w")
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(match_operand:SVE_F 3 "register_operand" "w, 0, w, w, w")]
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UNSPEC_COND_FSUB)]
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UNSPEC_COND_FABS)
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(match_operand:SVE_F 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& !rtx_equal_p (operands[2], operands[4])
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&& !rtx_equal_p (operands[3], operands[4])
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&& aarch64_sve_pred_dominates_p (&operands[5], operands[1])
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&& aarch64_sve_pred_dominates_p (&operands[7], operands[1])"
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"@
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movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;fabd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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#"
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"&& 1"
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{
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if (reload_completed
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&& register_operand (operands[4], <MODE>mode)
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&& !rtx_equal_p (operands[0], operands[4]))
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{
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emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3],
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operands[4], operands[1]));
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operands[4] = operands[3] = operands[0];
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}
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else if (!rtx_equal_p (operands[1], operands[5])
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|| !rtx_equal_p (operands[1], operands[7]))
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{
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operands[5] = copy_rtx (operands[1]);
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operands[7] = copy_rtx (operands[1]);
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}
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else
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FAIL;
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}
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[(set_attr "movprfx" "yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [FP] Multiplication
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;; -------------------------------------------------------------------------
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* gcc.target/aarch64/sve/cond_fabd_1.c: New test.
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* gcc.target/aarch64/sve/cond_fabd_1_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_2.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_2_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_3.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_3_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_4.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_4_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_5.c: Likewise.
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* gcc.target/aarch64/sve/cond_fabd_5_run.c: Likewise.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -0,0 +1,29 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE, ABS) \
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void __attribute__ ((noinline, noclone)) \
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test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict b, TYPE *__restrict c, \
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int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = a[i] < 20 ? ABS (b[i] - c[i]) : b[i]; \
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}
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#define TEST_ALL(T) \
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T (_Float16, __builtin_fabsf16) \
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T (float, __builtin_fabsf) \
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T (double, __builtin_fabs)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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@ -0,0 +1,33 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include "cond_fabd_1.c"
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#define N 99
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#define TEST_LOOP(TYPE, ABS) \
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{ \
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TYPE r[N], a[N], b[N], c[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i); \
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b[i] = (i >> 4) << (i & 15); \
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c[i] = ((i + 2) % 3) * (i + 1); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE (r, a, b, c, N); \
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for (int i = 0; i < N; ++i) \
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{ \
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TYPE expected = a[i] < 20 ? ABS (b[i] - c[i]) : b[i]; \
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if (r[i] != expected) \
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__builtin_abort (); \
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asm volatile ("" ::: "memory"); \
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} \
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}
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int
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main (void)
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE, ABS) \
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void __attribute__ ((noinline, noclone)) \
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test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict b, TYPE *__restrict c, \
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int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = a[i] < 20 ? ABS (b[i] - c[i]) : c[i]; \
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}
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#define TEST_ALL(T) \
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T (_Float16, __builtin_fabsf16) \
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T (float, __builtin_fabsf) \
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T (double, __builtin_fabs)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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@ -0,0 +1,33 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include "cond_fabd_2.c"
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#define N 99
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#define TEST_LOOP(TYPE, ABS) \
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{ \
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TYPE r[N], a[N], b[N], c[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i); \
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b[i] = (i >> 4) << (i & 15); \
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c[i] = ((i + 2) % 3) * (i + 1); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE (r, a, b, c, N); \
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for (int i = 0; i < N; ++i) \
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{ \
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TYPE expected = a[i] < 20 ? ABS (b[i] - c[i]) : c[i]; \
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if (r[i] != expected) \
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__builtin_abort (); \
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asm volatile ("" ::: "memory"); \
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} \
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}
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int
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main (void)
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE, ABS) \
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void __attribute__ ((noinline, noclone)) \
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test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict b, TYPE *__restrict c, \
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int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = a[i] < 20 ? ABS (b[i] - c[i]) : a[i]; \
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}
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#define TEST_ALL(T) \
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T (_Float16, __builtin_fabsf16) \
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T (float, __builtin_fabsf) \
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T (double, __builtin_fabs)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
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#include "cond_fabd_3.c"
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#define N 99
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#define TEST_LOOP(TYPE, ABS) \
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{ \
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TYPE r[N], a[N], b[N], c[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i); \
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b[i] = (i >> 4) << (i & 15); \
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c[i] = ((i + 2) % 3) * (i + 1); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE (r, a, b, c, N); \
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for (int i = 0; i < N; ++i) \
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{ \
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TYPE expected = a[i] < 20 ? ABS (b[i] - c[i]) : a[i]; \
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if (r[i] != expected) \
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__builtin_abort (); \
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asm volatile ("" ::: "memory"); \
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} \
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}
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int
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main (void)
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DEF_LOOP(TYPE, ABS) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \
|
||||
TYPE *__restrict b, TYPE *__restrict c, \
|
||||
int n) \
|
||||
{ \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
r[i] = a[i] < 20 ? ABS (b[i] - c[i]) : 8.0; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (_Float16, __builtin_fabsf16) \
|
||||
T (float, __builtin_fabsf) \
|
||||
T (double, __builtin_fabs)
|
||||
|
||||
TEST_ALL (DEF_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
|
||||
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsel\t} 3 } } */
|
|
@ -0,0 +1,33 @@
|
|||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
|
||||
|
||||
#include "cond_fabd_4.c"
|
||||
|
||||
#define N 99
|
||||
|
||||
#define TEST_LOOP(TYPE, ABS) \
|
||||
{ \
|
||||
TYPE r[N], a[N], b[N], c[N]; \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
{ \
|
||||
a[i] = (i & 1 ? i : 3 * i); \
|
||||
b[i] = (i >> 4) << (i & 15); \
|
||||
c[i] = ((i + 2) % 3) * (i + 1); \
|
||||
asm volatile ("" ::: "memory"); \
|
||||
} \
|
||||
test_##TYPE (r, a, b, c, N); \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
{ \
|
||||
TYPE expected = a[i] < 20 ? ABS (b[i] - c[i]) : 8; \
|
||||
if (r[i] != expected) \
|
||||
__builtin_abort (); \
|
||||
asm volatile ("" ::: "memory"); \
|
||||
} \
|
||||
}
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
TEST_ALL (TEST_LOOP)
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,35 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DEF_LOOP(TYPE, ABS) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \
|
||||
TYPE *__restrict b, TYPE *__restrict c, \
|
||||
int n) \
|
||||
{ \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
r[i] = a[i] < 20 ? ABS (b[i] - c[i]) : 0.0; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (_Float16, __builtin_fabsf16) \
|
||||
T (float, __builtin_fabsf) \
|
||||
T (double, __builtin_fabs)
|
||||
|
||||
TEST_ALL (DEF_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
|
||||
|
||||
/* Really we should be able to use MOVPRFX /Z here, but at the moment
|
||||
we're relying on combine to merge a SEL and an arithmetic operation,
|
||||
and the SEL doesn't allow zero operands. */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 1 { xfail *-*-* } } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 { xfail *-*-* } } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z, z[0-9]+\.d\n} 1 { xfail *-*-* } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */
|
|
@ -0,0 +1,33 @@
|
|||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
|
||||
|
||||
#include "cond_fabd_5.c"
|
||||
|
||||
#define N 99
|
||||
|
||||
#define TEST_LOOP(TYPE, ABS) \
|
||||
{ \
|
||||
TYPE r[N], a[N], b[N], c[N]; \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
{ \
|
||||
a[i] = (i & 1 ? i : 3 * i); \
|
||||
b[i] = (i >> 4) << (i & 15); \
|
||||
c[i] = ((i + 2) % 3) * (i + 1); \
|
||||
asm volatile ("" ::: "memory"); \
|
||||
} \
|
||||
test_##TYPE (r, a, b, c, N); \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
{ \
|
||||
TYPE expected = a[i] < 20 ? ABS (b[i] - c[i]) : 0; \
|
||||
if (r[i] != expected) \
|
||||
__builtin_abort (); \
|
||||
asm volatile ("" ::: "memory"); \
|
||||
} \
|
||||
}
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
TEST_ALL (TEST_LOOP)
|
||||
return 0;
|
||||
}
|
Loading…
Reference in New Issue