rs6000.c (rs6000_expand_vector_init): Use gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf...
gcc: 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf; remove element index adjustment for endian (now handled in vsx.md and altivec.md). (altivec_expand_vec_perm_const): Use gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw]. * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec. (vsx_xxspltw_<mode>): Adjust element index for little endian. * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a define_expand and a new define_insn *altivec_vspltb_internal; adjust for -maltivec=be on a little endian target. (altivec_vspltb_direct): New. (altivec_vsplth): Divide into a define_expand and a new define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a little endian target. (altivec_vsplth_direct): New. (altivec_vspltw): Divide into a define_expand and a new define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a little endian target. (altivec_vspltw_direct): New. (altivec_vspltsf): Divide into a define_expand and a new define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on a little endian target. gcc/testsuite: 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.dg/vmx/splat.c: New. * gcc.dg/vmx/splat-vsx.c: New. * gcc.dg/vmx/splat-be-order.c: New. * gcc.dg/vmx/splat-vsx-be-order.c: New. * gcc.dg/vmx/eg-5.c: Remove special casing for little endian. * gcc.dg/vmx/sn7153.c: Add special casing for little endian. From-SVN: r207318
This commit is contained in:
Bill Schmidt
William Schmidt
parent
c965e18748
commit
bf53d4b89e
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@ -1,3 +1,29 @@
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2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use
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gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf;
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remove element index adjustment for endian (now handled in vsx.md
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and altivec.md).
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(altivec_expand_vec_perm_const): Use
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gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw].
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* gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec.
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(vsx_xxspltw_<mode>): Adjust element index for little endian.
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* gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a
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define_expand and a new define_insn *altivec_vspltb_internal;
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adjust for -maltivec=be on a little endian target.
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(altivec_vspltb_direct): New.
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(altivec_vsplth): Divide into a define_expand and a new
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define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a
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little endian target.
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(altivec_vsplth_direct): New.
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(altivec_vspltw): Divide into a define_expand and a new
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define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a
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little endian target.
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(altivec_vspltw_direct): New.
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(altivec_vspltsf): Divide into a define_expand and a new
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define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on
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a little endian target.
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2014-01-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/59993
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@ -1600,44 +1600,187 @@
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"vsumsws %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vspltb"
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(define_expand "altivec_vspltb"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:QI 2 "u5bit_cint_operand" "")]
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"TARGET_ALTIVEC"
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{
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rtvec v;
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rtx x;
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/* Special handling for LE with -maltivec=be. We have to reflect
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the actual selected index for the splat in the RTL. */
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if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
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operands[2] = GEN_INT (15 - INTVAL (operands[2]));
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v = gen_rtvec (1, operands[2]);
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x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
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x = gen_rtx_VEC_DUPLICATE (V16QImode, x);
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
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DONE;
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})
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(define_insn "*altivec_vspltb_internal"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(vec_duplicate:V16QI
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(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
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(parallel
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[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
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"TARGET_ALTIVEC"
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{
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/* For true LE, this adjusts the selected index. For LE with
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-maltivec=be, this reverses what was done in the define_expand
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because the instruction already has big-endian bias. */
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if (!BYTES_BIG_ENDIAN)
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operands[2] = GEN_INT (15 - INTVAL (operands[2]));
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return "vspltb %0,%1,%2";
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}
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vspltb_direct"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
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(match_operand:QI 2 "u5bit_cint_operand" "i")]
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UNSPEC_VSPLT_DIRECT))]
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"TARGET_ALTIVEC"
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"vspltb %0,%1,%2"
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vsplth"
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(define_expand "altivec_vsplth"
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[(match_operand:V8HI 0 "register_operand" "")
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(match_operand:V8HI 1 "register_operand" "")
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(match_operand:QI 2 "u5bit_cint_operand" "")]
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"TARGET_ALTIVEC"
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{
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rtvec v;
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rtx x;
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/* Special handling for LE with -maltivec=be. We have to reflect
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the actual selected index for the splat in the RTL. */
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if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
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operands[2] = GEN_INT (7 - INTVAL (operands[2]));
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v = gen_rtvec (1, operands[2]);
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x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
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x = gen_rtx_VEC_DUPLICATE (V8HImode, x);
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
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DONE;
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})
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(define_insn "*altivec_vsplth_internal"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(vec_duplicate:V8HI
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(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
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(parallel
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[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
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"TARGET_ALTIVEC"
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{
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/* For true LE, this adjusts the selected index. For LE with
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-maltivec=be, this reverses what was done in the define_expand
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because the instruction already has big-endian bias. */
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if (!BYTES_BIG_ENDIAN)
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operands[2] = GEN_INT (7 - INTVAL (operands[2]));
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return "vsplth %0,%1,%2";
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}
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vsplth_direct"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
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(match_operand:QI 2 "u5bit_cint_operand" "i")]
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UNSPEC_VSPLT_DIRECT))]
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"TARGET_ALTIVEC"
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"vsplth %0,%1,%2"
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vspltw"
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(define_expand "altivec_vspltw"
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[(match_operand:V4SI 0 "register_operand" "")
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(match_operand:V4SI 1 "register_operand" "")
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(match_operand:QI 2 "u5bit_cint_operand" "")]
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"TARGET_ALTIVEC"
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{
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rtvec v;
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rtx x;
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/* Special handling for LE with -maltivec=be. We have to reflect
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the actual selected index for the splat in the RTL. */
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if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
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operands[2] = GEN_INT (3 - INTVAL (operands[2]));
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v = gen_rtvec (1, operands[2]);
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x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
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x = gen_rtx_VEC_DUPLICATE (V4SImode, x);
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
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DONE;
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})
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(define_insn "*altivec_vspltw_internal"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_duplicate:V4SI
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(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
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(parallel
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[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
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"TARGET_ALTIVEC"
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{
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/* For true LE, this adjusts the selected index. For LE with
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-maltivec=be, this reverses what was done in the define_expand
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because the instruction already has big-endian bias. */
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if (!BYTES_BIG_ENDIAN)
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operands[2] = GEN_INT (3 - INTVAL (operands[2]));
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return "vspltw %0,%1,%2";
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}
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vspltw_direct"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:QI 2 "u5bit_cint_operand" "i")]
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UNSPEC_VSPLT_DIRECT))]
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"TARGET_ALTIVEC"
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"vspltw %0,%1,%2"
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vspltsf"
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(define_expand "altivec_vspltsf"
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[(match_operand:V4SF 0 "register_operand" "")
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(match_operand:V4SF 1 "register_operand" "")
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(match_operand:QI 2 "u5bit_cint_operand" "")]
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"TARGET_ALTIVEC"
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{
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rtvec v;
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rtx x;
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/* Special handling for LE with -maltivec=be. We have to reflect
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the actual selected index for the splat in the RTL. */
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if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
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operands[2] = GEN_INT (3 - INTVAL (operands[2]));
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v = gen_rtvec (1, operands[2]);
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x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
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x = gen_rtx_VEC_DUPLICATE (V4SFmode, x);
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
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DONE;
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})
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(define_insn "*altivec_vspltsf_internal"
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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(vec_duplicate:V4SF
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(vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
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(parallel
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[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
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"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
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"vspltw %0,%1,%2"
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{
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/* For true LE, this adjusts the selected index. For LE with
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-maltivec=be, this reverses what was done in the define_expand
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because the instruction already has big-endian bias. */
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if (!BYTES_BIG_ENDIAN)
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operands[2] = GEN_INT (3 - INTVAL (operands[2]));
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return "vspltw %0,%1,%2";
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}
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vspltis<VI_char>"
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@ -5485,7 +5485,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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: gen_vsx_xscvdpsp_scalar (freg, sreg));
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emit_insn (cvt);
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emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
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emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx));
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}
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else
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{
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@ -5522,11 +5522,9 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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gen_rtx_SET (VOIDmode,
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target, mem),
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x)));
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field = (BYTES_BIG_ENDIAN ? const0_rtx
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: GEN_INT (GET_MODE_NUNITS (mode) - 1));
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x = gen_rtx_VEC_SELECT (inner_mode, target,
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gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (1, field)));
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gen_rtvec (1, const0_rtx)));
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emit_insn (gen_rtx_SET (VOIDmode, target,
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gen_rtx_VEC_DUPLICATE (mode, x)));
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return;
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@ -29980,7 +29978,7 @@ altivec_expand_vec_perm_const (rtx operands[4])
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{
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if (!BYTES_BIG_ENDIAN)
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elt = 15 - elt;
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emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
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emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
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return true;
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}
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@ -29993,8 +29991,8 @@ altivec_expand_vec_perm_const (rtx operands[4])
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{
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int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
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x = gen_reg_rtx (V8HImode);
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emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
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GEN_INT (field)));
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emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
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GEN_INT (field)));
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emit_move_insn (target, gen_lowpart (V16QImode, x));
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return true;
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}
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@ -30012,8 +30010,8 @@ altivec_expand_vec_perm_const (rtx operands[4])
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{
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int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
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x = gen_reg_rtx (V4SImode);
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emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
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GEN_INT (field)));
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emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
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GEN_INT (field)));
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emit_move_insn (target, gen_lowpart (V16QImode, x));
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return true;
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}
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@ -213,6 +213,7 @@
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UNSPEC_VSX_ROUND_I
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UNSPEC_VSX_ROUND_IC
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UNSPEC_VSX_SLDWI
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UNSPEC_VSX_XXSPLTW
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])
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;; VSX moves
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@ -1751,6 +1752,20 @@
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(parallel
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[(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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if (!BYTES_BIG_ENDIAN)
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operands[2] = GEN_INT (3 - INTVAL (operands[2]));
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return "xxspltw %x0,%x1,%2";
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}
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[(set_attr "type" "vecperm")])
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(define_insn "vsx_xxspltw_<mode>_direct"
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[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
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(unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
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(match_operand:QI 2 "u5bit_cint_operand" "i,i")]
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UNSPEC_VSX_XXSPLTW))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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"xxspltw %x0,%x1,%2"
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[(set_attr "type" "vecperm")])
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@ -1,3 +1,12 @@
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2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* gcc.dg/vmx/splat.c: New.
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* gcc.dg/vmx/splat-vsx.c: New.
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* gcc.dg/vmx/splat-be-order.c: New.
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* gcc.dg/vmx/splat-vsx-be-order.c: New.
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* gcc.dg/vmx/eg-5.c: Remove special casing for little endian.
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* gcc.dg/vmx/sn7153.c: Add special casing for little endian.
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2014-01-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/59993
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@ -6,19 +6,10 @@ matvecmul4 (vector float c0, vector float c1, vector float c2,
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{
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/* Set result to a vector of f32 0's */
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vector float result = ((vector float){0.,0.,0.,0.});
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#ifdef __LITTLE_ENDIAN__
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result = vec_madd (c0, vec_splat (v, 3), result);
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result = vec_madd (c1, vec_splat (v, 2), result);
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result = vec_madd (c2, vec_splat (v, 1), result);
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result = vec_madd (c3, vec_splat (v, 0), result);
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#else
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result = vec_madd (c0, vec_splat (v, 0), result);
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result = vec_madd (c1, vec_splat (v, 1), result);
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result = vec_madd (c2, vec_splat (v, 2), result);
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result = vec_madd (c3, vec_splat (v, 3), result);
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#endif
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return result;
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}
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@ -34,7 +34,11 @@ main()
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void validate_sat()
|
||||
{
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
if (vec_any_ne(vec_splat(vec_mfvscr(), 0), ((vector unsigned short){1,1,1,1,1,1,1,1})))
|
||||
#else
|
||||
if (vec_any_ne(vec_splat(vec_mfvscr(), 7), ((vector unsigned short){1,1,1,1,1,1,1,1})))
|
||||
#endif
|
||||
{
|
||||
union {vector unsigned short v; unsigned short s[8];} u;
|
||||
u.v = vec_mfvscr();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
|
||||
|
||||
#include "harness.h"
|
||||
|
||||
static void test()
|
||||
{
|
||||
/* Input vectors. */
|
||||
vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
|
||||
vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
|
||||
vector unsigned short vus = {0,1,2,3,4,5,6,7};
|
||||
vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
|
||||
vector unsigned int vui = {0,1,2,3};
|
||||
vector signed int vsi = {-2,-1,0,1};
|
||||
vector float vf = {-2.0,-1.0,0.0,1.0};
|
||||
|
||||
/* Result vectors. */
|
||||
vector unsigned char vucr;
|
||||
vector signed char vscr;
|
||||
vector unsigned short vusr;
|
||||
vector signed short vssr;
|
||||
vector unsigned int vuir;
|
||||
vector signed int vsir;
|
||||
vector float vfr;
|
||||
|
||||
/* Expected result vectors. */
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
vector unsigned char vucer = {14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14};
|
||||
vector signed char vscer = {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};
|
||||
vector unsigned short vuser = {0,0,0,0,0,0,0,0};
|
||||
vector signed short vsser = {3,3,3,3,3,3,3,3};
|
||||
vector unsigned int vuier = {1,1,1,1};
|
||||
vector signed int vsier = {-2,-2,-2,-2};
|
||||
vector float vfer = {0.0,0.0,0.0,0.0};
|
||||
#else
|
||||
vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
|
||||
vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
vector unsigned short vuser = {7,7,7,7,7,7,7,7};
|
||||
vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};
|
||||
vector unsigned int vuier = {2,2,2,2};
|
||||
vector signed int vsier = {1,1,1,1};
|
||||
vector float vfer = {-1.0,-1.0,-1.0,-1.0};
|
||||
#endif
|
||||
|
||||
vucr = vec_splat (vuc, 1);
|
||||
vscr = vec_splat (vsc, 8);
|
||||
vusr = vec_splat (vus, 7);
|
||||
vssr = vec_splat (vss, 0);
|
||||
vuir = vec_splat (vui, 2);
|
||||
vsir = vec_splat (vsi, 3);
|
||||
vfr = vec_splat (vf, 1);
|
||||
|
||||
check (vec_all_eq (vucr, vucer), "vuc");
|
||||
check (vec_all_eq (vscr, vscer), "vsc");
|
||||
check (vec_all_eq (vusr, vuser), "vus");
|
||||
check (vec_all_eq (vssr, vsser), "vss");
|
||||
check (vec_all_eq (vuir, vuier), "vui");
|
||||
check (vec_all_eq (vsir, vsier), "vsi");
|
||||
check (vec_all_eq (vfr, vfer ), "vf");
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
|
||||
|
||||
#include "harness.h"
|
||||
|
||||
static void test()
|
||||
{
|
||||
/* Input vectors. */
|
||||
vector unsigned int vui = {0,1,2,3};
|
||||
vector signed int vsi = {-2,-1,0,1};
|
||||
vector float vf = {-2.0,-1.0,0.0,1.0};
|
||||
|
||||
/* Result vectors. */
|
||||
vector unsigned int vuir;
|
||||
vector signed int vsir;
|
||||
vector float vfr;
|
||||
|
||||
/* Expected result vectors. */
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
vector unsigned int vuier = {1,1,1,1};
|
||||
vector signed int vsier = {-2,-2,-2,-2};
|
||||
vector float vfer = {0.0,0.0,0.0,0.0};
|
||||
#else
|
||||
vector unsigned int vuier = {2,2,2,2};
|
||||
vector signed int vsier = {1,1,1,1};
|
||||
vector float vfer = {-1.0,-1.0,-1.0,-1.0};
|
||||
#endif
|
||||
|
||||
vuir = vec_splat (vui, 2);
|
||||
vsir = vec_splat (vsi, 3);
|
||||
vfr = vec_splat (vf, 1);
|
||||
|
||||
check (vec_all_eq (vuir, vuier), "vui");
|
||||
check (vec_all_eq (vsir, vsier), "vsi");
|
||||
check (vec_all_eq (vfr, vfer ), "vf");
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
|
||||
|
||||
#include "harness.h"
|
||||
|
||||
static void test()
|
||||
{
|
||||
/* Input vectors. */
|
||||
vector unsigned int vui = {0,1,2,3};
|
||||
vector signed int vsi = {-2,-1,0,1};
|
||||
vector float vf = {-2.0,-1.0,0.0,1.0};
|
||||
|
||||
/* Result vectors. */
|
||||
vector unsigned int vuir;
|
||||
vector signed int vsir;
|
||||
vector float vfr;
|
||||
|
||||
/* Expected result vectors. */
|
||||
vector unsigned int vuier = {2,2,2,2};
|
||||
vector signed int vsier = {1,1,1,1};
|
||||
vector float vfer = {-1.0,-1.0,-1.0,-1.0};
|
||||
|
||||
vuir = vec_splat (vui, 2);
|
||||
vsir = vec_splat (vsi, 3);
|
||||
vfr = vec_splat (vf, 1);
|
||||
|
||||
check (vec_all_eq (vuir, vuier), "vui");
|
||||
check (vec_all_eq (vsir, vsier), "vsi");
|
||||
check (vec_all_eq (vfr, vfer ), "vf");
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#include "harness.h"
|
||||
|
||||
static void test()
|
||||
{
|
||||
/* Input vectors. */
|
||||
vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
|
||||
vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
|
||||
vector unsigned short vus = {0,1,2,3,4,5,6,7};
|
||||
vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
|
||||
vector unsigned int vui = {0,1,2,3};
|
||||
vector signed int vsi = {-2,-1,0,1};
|
||||
vector float vf = {-2.0,-1.0,0.0,1.0};
|
||||
|
||||
/* Result vectors. */
|
||||
vector unsigned char vucr;
|
||||
vector signed char vscr;
|
||||
vector unsigned short vusr;
|
||||
vector signed short vssr;
|
||||
vector unsigned int vuir;
|
||||
vector signed int vsir;
|
||||
vector float vfr;
|
||||
|
||||
/* Expected result vectors. */
|
||||
vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
|
||||
vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
vector unsigned short vuser = {7,7,7,7,7,7,7,7};
|
||||
vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};
|
||||
vector unsigned int vuier = {2,2,2,2};
|
||||
vector signed int vsier = {1,1,1,1};
|
||||
vector float vfer = {-1.0,-1.0,-1.0,-1.0};
|
||||
|
||||
vucr = vec_splat (vuc, 1);
|
||||
vscr = vec_splat (vsc, 8);
|
||||
vusr = vec_splat (vus, 7);
|
||||
vssr = vec_splat (vss, 0);
|
||||
vuir = vec_splat (vui, 2);
|
||||
vsir = vec_splat (vsi, 3);
|
||||
vfr = vec_splat (vf, 1);
|
||||
|
||||
check (vec_all_eq (vucr, vucer), "vuc");
|
||||
check (vec_all_eq (vscr, vscer), "vsc");
|
||||
check (vec_all_eq (vusr, vuser), "vus");
|
||||
check (vec_all_eq (vssr, vsser), "vss");
|
||||
check (vec_all_eq (vuir, vuier), "vui");
|
||||
check (vec_all_eq (vsir, vsier), "vsi");
|
||||
check (vec_all_eq (vfr, vfer ), "vf");
|
||||
}
|
||||
Loading…
Reference in New Issue