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re PR target/17984 (Recent peephole2:s may cause internal compiler errors (2)) 

PR target/17984
	* config/cris/cris.md (asrandb, asrandw, lsrandb, lsrandw): Apply
	trunc_int_for_mode for constants used in shortened mode.

From-SVN: r89011
This commit is contained in:
Hans-Peter Nilsson 2004-10-13 23:35:03 +00:00 committed by Hans-Peter Nilsson
parent 5a78838a41
commit bf6ac87cc8
2 changed files with 26 additions and 8 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2004-10-14 Hans-Peter Nilsson <hp@axis.com>
PR target/17984
* config/cris/cris.md (asrandb, asrandw, lsrandb, lsrandw): Apply
trunc_int_for_mode for constants used in shortened mode.
2004-10-13 Richard Henderson <rth@redhat.com>
PR c/17384

28
gcc/config/cris/cris.md
View File

@ -4717,9 +4717,12 @@
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
(set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
"operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
{
operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
})
(define_peephole2 ; asrandw (peephole casesi+32)
[(set (match_operand:SI 0 "register_operand" "")
@ -4735,9 +4738,12 @@
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
(set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
"operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
{
operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
})
(define_peephole2 ; lsrandb (peephole casesi+33)
[(set (match_operand:SI 0 "register_operand" "")
@ -4749,9 +4755,12 @@
&& INTVAL (operands[2]) < 255
&& INTVAL (operands[1]) > 23"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
(set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
"operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
{
operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
})
(define_peephole2 ; lsrandw (peephole casesi+34)
[(set (match_operand:SI 0 "register_operand" "")
@ -4763,9 +4772,12 @@
&& INTVAL (operands[2]) != 255
&& INTVAL (operands[1]) > 15"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
(set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
"operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
{
operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
})
;; Change