arm: Auto-vectorization for MVE: vshr
This patch enables MVE vshr instructions for auto-vectorization. New MVE patterns are introduced that take a vector of constants as second operand, all constants being equal. The existing mve_vshrq_n_<supf><mode> is kept, as it takes a single immediate as second operand, and is used by arm_mve.h. The vashr<mode>3 and vlshr<mode>3 expanders are moved fron neon.md to vec-common.md, updated to rely on the normal expansion scheme to generate shifts by immediate. 2020-12-03 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/mve.md (mve_vshrq_n_s<mode>_imm): New entry. (mve_vshrq_n_u<mode>_imm): Likewise. * config/arm/neon.md (vashr<mode>3, vlshr<mode>3): Move to ... * config/arm/vec-common.md: ... here. gcc/testsuite/ * gcc.target/arm/simd/mve-vshr.c: Add tests for vshr.
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Christophe Lyon
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@ -763,6 +763,7 @@
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;;
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;; [vshrq_n_s, vshrq_n_u])
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;;
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;; Version that takes an immediate as operand 2.
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(define_insn "mve_vshrq_n_<supf><mode>"
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[
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(set (match_operand:MVE_2 0 "s_register_operand" "=w")
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@ -775,6 +776,39 @@
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[(set_attr "type" "mve_move")
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])
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;; Versions that take constant vectors as operand 2 (with all elements
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;; equal).
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(define_insn "mve_vshrq_n_s<mode>_imm"
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[
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(set (match_operand:MVE_2 0 "s_register_operand" "=w")
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(ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
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]
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"TARGET_HAVE_MVE"
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{
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return neon_output_shift_immediate ("vshr", 's', &operands[2],
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<MODE>mode,
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VALID_NEON_QREG_MODE (<MODE>mode),
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true);
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}
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[(set_attr "type" "mve_move")
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])
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(define_insn "mve_vshrq_n_u<mode>_imm"
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[
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(set (match_operand:MVE_2 0 "s_register_operand" "=w")
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(lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
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]
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"TARGET_HAVE_MVE"
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{
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return neon_output_shift_immediate ("vshr", 'u', &operands[2],
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<MODE>mode,
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VALID_NEON_QREG_MODE (<MODE>mode),
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true);
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}
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
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;;
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@ -899,40 +899,6 @@
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[(set_attr "type" "neon_shift_reg<q>")]
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)
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(define_expand "vashr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand")
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(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
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"TARGET_NEON"
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{
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if (s_register_operand (operands[2], <MODE>mode))
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neon_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
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}
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else
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emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "vlshr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand")
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(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
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"TARGET_NEON"
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{
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if (s_register_operand (operands[2], <MODE>mode))
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neon_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
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}
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else
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emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; 64-bit shifts
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;; This pattern loads a 32-bit shift count into a 64-bit NEON register,
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@ -259,4 +259,40 @@
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{
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emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], operands[2]));
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DONE;
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})
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})
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;; When operand 2 is an immediate, use the normal expansion to match
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;; gen_vashr<mode>3_imm for Neon and gen_mve_vshrq_n_s<mode>_imm for
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;; MVE.
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(define_expand "vashr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand")
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(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
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"ARM_HAVE_<MODE>_ARITH"
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{
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if (s_register_operand (operands[2], <MODE>mode))
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_mve_vshlq_s<mode> (operands[0], operands[1], neg));
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DONE;
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}
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})
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;; When operand 2 is an immediate, use the normal expansion to match
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;; gen_vashr<mode>3_imm for Neon and gen_mve_vshrq_n_u<mode>_imm for
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;; MVE.
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(define_expand "vlshr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand")
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(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
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"ARM_HAVE_<MODE>_ARITH"
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{
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if (s_register_operand (operands[2], <MODE>mode))
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], neg));
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DONE;
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}
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})
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59
gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
Normal file
59
gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
Normal file
@ -0,0 +1,59 @@
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/* { dg-do assemble } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-add-options arm_v8_1m_mve } */
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/* { dg-additional-options "-O3" } */
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#include <stdint.h>
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#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \
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void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
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int i; \
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for (i=0; i<NB; i++) { \
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dest[i] = a[i] OP b[i]; \
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} \
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}
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#define FUNC_IMM(SIGN, TYPE, BITS, NB, OP, NAME) \
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void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \
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int i; \
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for (i=0; i<NB; i++) { \
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dest[i] = a[i] OP 5; \
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} \
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}
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/* 64-bit vectors. */
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FUNC(s, int, 32, 2, >>, vshr)
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FUNC(u, uint, 32, 2, >>, vshr)
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FUNC(s, int, 16, 4, >>, vshr)
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FUNC(u, uint, 16, 4, >>, vshr)
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FUNC(s, int, 8, 8, >>, vshr)
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FUNC(u, uint, 8, 8, >>, vshr)
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/* 128-bit vectors. */
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FUNC(s, int, 32, 4, >>, vshr)
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FUNC(u, uint, 32, 4, >>, vshr)
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FUNC(s, int, 16, 8, >>, vshr)
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FUNC(u, uint, 16, 8, >>, vshr)
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FUNC(s, int, 8, 16, >>, vshr)
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FUNC(u, uint, 8, 16, >>, vshr)
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/* 64-bit vectors. */
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FUNC_IMM(s, int, 32, 2, >>, vshrimm)
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FUNC_IMM(u, uint, 32, 2, >>, vshrimm)
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FUNC_IMM(s, int, 16, 4, >>, vshrimm)
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FUNC_IMM(u, uint, 16, 4, >>, vshrimm)
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FUNC_IMM(s, int, 8, 8, >>, vshrimm)
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FUNC_IMM(u, uint, 8, 8, >>, vshrimm)
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/* 128-bit vectors. */
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FUNC_IMM(s, int, 32, 4, >>, vshrimm)
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FUNC_IMM(u, uint, 32, 4, >>, vshrimm)
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FUNC_IMM(s, int, 16, 8, >>, vshrimm)
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FUNC_IMM(u, uint, 16, 8, >>, vshrimm)
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FUNC_IMM(s, int, 8, 16, >>, vshrimm)
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FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
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/* MVE has only 128-bit vectors, so we can vectorize only half of the
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functions above. */
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/* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
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/* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
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